Z8F0813HJ005EG Zilog, Z8F0813HJ005EG Datasheet - Page 69

• Manufacturer Part Number: Z8F0813HJ005EG
• Description: IC Z8 ENCORE MCU FLASH 8K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0813HJ005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4182; Z8F0813HJ005EG

Interrupt Control Register Definitions
PS025203-0405
Caution:
Caution:
Caution:
Software Interrupt Assertion
Interrupt Request 0 Register
Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
For all interrupts other than the Watch-Dog Timer interrupt, the Primary Oscillator Fail
Trap, and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individ-
ual interrupts, set interrupt priorities, and indicate interrupt requests.
The Interrupt Request 0 (IRQ0) register (Table 34) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 register to determine if any interrupt requests are pending.
The following coding style used to generate software interrupts by setting bits in the In-
terrupt Request registers is NOT recommended. All incoming interrupts received be-
tween execution of the first LDX command and the final LDX command are lost.
To avoid missing interrupts, use the following coding style to set bits in the Interrupt Re-
quest registers:
To avoid missing interrupts, use the following coding style to clear bits in
the Interrupt Request 0 register:
Good coding style that avoids lost interrupt requests:
Poor coding style that can result in lost interrupt requests:
Good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
P R E L I M I N A R Y
Z8 Encore!
Product Specification
®
Z8F0823 Series
Interrupt Controller
52