ATMEGA2561V-8AU Atmel, ATMEGA2561V-8AU Datasheet - Page 440
![IC AVR MCU 256K 8MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA2561V-8AU
Manufacturer Part Number
ATMEGA2561V-8AU
Description
IC AVR MCU 256K 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA2561V-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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2549M–AVR–09/10
23 2-wire Serial Interface .......................................................................... 241
24 AC – Analog Comparator .................................................................... 271
25 ADC – Analog to Digital Converter ..................................................... 275
26 JTAG Interface and On-chip Debug System ..................................... 296
27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 302
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
24.1
24.2
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
27.1
27.2
Features ........................................................................................................241
2-wire Serial Interface Bus Definition ............................................................241
Data Transfer and Frame Format ..................................................................242
Multi-master Bus Systems, Arbitration and Synchronization .........................245
Overview of the TWI Module .........................................................................246
Using the TWI ................................................................................................249
Transmission Modes .....................................................................................252
Multi-master Systems and Arbitration ............................................................265
Register Description ......................................................................................266
Analog Comparator Multiplexed Input ...........................................................271
Register Description ......................................................................................272
Features ........................................................................................................275
Operation .......................................................................................................276
Starting a Conversion ....................................................................................277
Prescaling and Conversion Timing ................................................................278
Changing Channel or Reference Selection ...................................................282
ADC Noise Canceler .....................................................................................283
ADC Conversion Result .................................................................................288
Register Description ......................................................................................289
Features ........................................................................................................296
Overview ........................................................................................................296
TAP - Test Access Port .................................................................................297
Using the Boundary-scan Chain ....................................................................299
Using the On-chip Debug System .................................................................299
On-chip Debug Specific JTAG Instructions ...................................................300
Using the JTAG Programming Capabilities ...................................................301
Bibliography ...................................................................................................301
On-chip Debug Related Register in I/O Memory ...........................................301
Features ........................................................................................................302
System Overview ...........................................................................................302
ATmega640/1280/1281/2560/2561
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