ATMEGA2561V-8AU Atmel, ATMEGA2561V-8AU Datasheet - Page 304
![IC AVR MCU 256K 8MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA2561V-8AU
Manufacturer Part Number
ATMEGA2561V-8AU
Description
IC AVR MCU 256K 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA2561V-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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- Download datasheet (10Mb)
27.3.4
27.4
27.4.1
27.4.2
2549M–AVR–09/10
Boundary-scan Specific JTAG Instructions
Boundary-scan Chain
EXTEST; 0x0
IDCODE; 0x1
Figure 27-2. Reset Register
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections.
See
The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the
JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction
is not implemented, but all outputs with tri-state capability can be set in high-impedant state by
using the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip
connections, the interface between the analog and the digital logic is in the scan chain. The con-
tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-
Register is loaded with the EXTEST instruction.
The active states are:
•
•
•
Optional JTAG instruction selecting the 32-bit ID-Register as Data Register. The ID-Register
consists of a version number, a device number and the manufacturer code chosen by JEDEC.
This is the default instruction after power-up.
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The Internal Scan Chain is shifted by the TCK input.
Update-DR: Data from the scan chain is applied to output pins.
“Boundary-scan Chain” on page 305
From Other Internal and
External Reset Sources
From
ClockDR · AVR_RESET
TDI
ATmega640/1280/1281/2560/2561
D
for a complete description.
Q
TDO
To
Internal reset
304
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