ATMEGA2561V-8AU Atmel, ATMEGA2561V-8AU Datasheet - Page 350
![IC AVR MCU 256K 8MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA2561V-8AU
Manufacturer Part Number
ATMEGA2561V-8AU
Description
IC AVR MCU 256K 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA2561V-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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29.8.1
29.8.2
2549M–AVR–09/10
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 29-15. Pin Mapping Serial Programming
Figure 29-10. Serial Programming and Verify
Notes:
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega640/1280/1281/2560/2561, data is clocked on the rising
edge of SCK.
When reading data from the ATmega640/1280/1281/2560/2561, data is clocked on the falling
edge of SCK. See
Symbol
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
PDO
SCK
PDI
XTAL1 pin.
programming the EEPROM, an auto-erase cycle is built into the self-timed programming oper-
ation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
CC
- 0.3V < AVCC < V
Figure 29-12 on page 353
(TQFP-100)
Pins
PB2
PB3
PB1
PDO
SCK
PDI
ck
ck
CC
ATmega640/1280/1281/2560/2561
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8V - 5.5V.When
XT AL1
RESET
GND
(TQFP-64)
for timing details.
(1)
Pins
PE0
PE1
PB1
AVCC
VCC
+1.8V - 5.5V
+1.8V - 5.5V
I/O
O
I
I
(2)
ck
ck
>= 12 MHz
>= 12 MHz
Serial Data out
Serial Data in
Description
Serial Clock
350
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