ATMEGA2561V-8AU Atmel, ATMEGA2561V-8AU Datasheet - Page 167
![IC AVR MCU 256K 8MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA2561V-8AU
Manufacturer Part Number
ATMEGA2561V-8AU
Description
IC AVR MCU 256K 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA2561V-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 167 of 444
- Download datasheet (10Mb)
16.11.37 TIFR1 – Timer/Counter1 Interrupt Flag Register
16.11.38 TIFR3 – Timer/Counter3 Interrupt Flag Register
16.11.39 TIFR4 – Timer/Counter4 Interrupt Flag Register
16.11.40 TIFR5 – Timer/Counter5 Interrupt Flag Register
2549M–AVR–09/10
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(see
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register
(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the coun-
ter reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-
cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
Bit
0x16 (0x36)
Read/Write
Initial Value
Bit
0x18 (0x38)
Read/Write
Initial Value
Bit
0x19 (0x39)
Read/Write
Initial Value
Bit
0x1A (0x3A)
Read/Write
Initial Value
“Interrupts” on page
R
R
R
R
7
–
0
7
–
0
7
–
0
7
–
0
“Interrupts” on page
105) is executed when the TOVn Flag, located in TIFRn, is set.
R
R
R
R
6
–
0
6
–
0
6
–
0
6
–
0
ATmega640/1280/1281/2560/2561
ICF1
ICF3
ICF4
ICF5
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
105) is executed when the OCFnA Flag, located in
R
R
R
R
4
–
0
4
–
0
4
–
0
4
–
0
OCF1C
OCF3C
OCF4C
OCF5C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCF1B
OCF3B
OCF4B
OCF5B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCF1A
OCF3A
OCF4A
OCF5A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOV1
TOV3
TOV4
TOV5
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TIFR1
TIFR3
TIFR4
TIFR5
167
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