ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 345
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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29.3
8077H–AVR–12/09
PDI Physical
(PDI_CLK), and the dedicated Test pin for data input and output (PDI_DATA). A JTAG interface
is also available on most devices, and this can be used for programming and debugging through
the 4-pin JTAG interface. The JTAG interface is IEEE std. 1149.1 compliant, and supports
boundary scan. Unless otherwise stated, all references to the PDI assumes access through the
PDI physical. Any external programmer or on-chip debugger/emulator can be directly connected
to these interfaces, and no external components are required.
Figure 29-1. The PDI with JTAG and PDI physical and closely related modules (grey)
The PDI physical layer handles the basic low-level serial communication. The physical layer
uses a bi-directional half-duplex synchronous serial receiver and transmitter (as a USART in
USRT mode). The physical layer includes start-of-frame detection, frame error detection, parity
generation, parity error detection, and collision detection.
The PDI is accessed through two pins:
In addition to these two pins, V
grammer/debugger and the device.
Figure 29-2. PDI connection
• PDI_CLK: PDI clock input (Reset pin).
• PDI_DATA: PDI data input/output (Test pin).
PDI_CLK
PDI_DATA
TDI
TMI
TCK
TDO
Program and Debug Interface (PDI)
Gnd
(physical layer)
(physical layer)
JTAG Physical
PDI Physical
Programmer/
Debugger
CC
and GND must also be connected between the External Pro-
Figure 29-2 on page 345
Controller
Vcc
PDI
PDI_CLK (RESET)
PDI_DATA (TEST)
shows a typical connection.
PDIBUS
Internal Interfaces
XMEGA A
Controller
Memories
OCD
NVM
NVM
345
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