ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 212

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

19.4
8077H–AVR–12/09
TWI Bus State Logic
device which first completes its high period (DEVICE1) forces the clock line low and the proce-
dure are then repeated. The result of this is that the device with the shortest clock period
determines the high period while the low period of the clock is determined by the longest clock
period.
The bus state logic continuously monitors the activity on the TWI bus lines when the master is
enabled. It continues to operate in all sleep modes, including Power down.
The bus state logic includes START and STOP condition detectors, collision detection, inactive
bus timeout detection, and bit counter. This is used to determine the bus state. Software can get
the current bus state by reading the Bus State bits in the Master Status register. The bus state
can be 'unknown', 'idle', 'busy' or 'owner' and is determined according to the state diagram
shown in
the figure.
Figure 19-11. Bus State, State Diagram
After a system reset, the bus state is unknown. From this the bus state machine can be forced to
enter idle by writing to the Bus State bits accordingly. If no state is set by application software
the bus state will become idle when a STOP condition is detected. If the Master Inactive Bus
Timeout is enabled the bus state will change to idle on the occurrence of a timeout. After a
known bus state is established the bus state will not re-enter the unknown state from any of the
other states. Only a system reset or disabling the TWI master will set the state to unknown.
When the bus is idle it is ready for a new transaction. If a START condition generated externally
is detected, the bus becomes busy until a STOP condition is detected. The STOP condition will
change the bus state to idle. If the Master Inactive Bus Timeout is enabled bus state will change
from busy to idle on the occurrence of a timeout.
Figure
19-11. The value of the Bus State bits according to state is shown in binary in
RESET
(0b01)
IDLE
P + Timeout
Write ADDRESS
UNKNOWN
(S)
(0b00)
Command P
P + Timeout
OWNER
(0b10)
S
ADDRESS(Sr)
Write
Arbitration
Lost
BUSY
(0b11)
Sr
XMEGA A
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