ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 179

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

15.4
8077H–AVR–12/09
Dead Time Insertion
The Dead Time Insertion (DTI) unit enables generation of “off” time where both the non-inverted
Low Side (LS) and inverted High Side (HS) of the WG output is low. This “off” time is called
dead-time, and dead-time insertion ensure that the LS and HS does not switch simultaneously.
The DTI unit consists of four equal dead time generators, one for each of the capture or com-
pare channel in Timer/Counter 0.
time generator. The dead time registers that define the number of peripheral clock cycles the
dead time is going to last, are common for all four channels. The High Side and Low Side can
have independent dead time setting and the dead time registers are double buffered.
Figure 15-3. Dead Time Generator block diagram
As shown in
one for each peripheral clock cycle until it reaches zero. A non-zero counter value will force both
the Low Side and High Side outputs into their “off” state. When a change is detected on the WG
output, the Dead Time Counter is reloaded with the DTx register value according to the edge of
the input. Positive edge initiates a counter reload of the DTLS Register and a negative edge a
reload of DTHS Register.
WG output
Dead Time Generator
Figure 15-4 on page
D
Q
Edge Detect
V
Figure 15-3 on page 179
180, the 8-bit Dead Time Counter (dti_cnt) is decremented by
DTLSBUF
DTILS
LOAD
E
V
shows the block diagram of one dead
Counter ("dti_cnt")
DTHSBUF
= 0
DTIHS
XMEGA A
"dtls"
(To PORT)
"dths"
(To PORT)
179