ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 272
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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24.6.5
24.6.6
24.7
24.7.1
8077H–AVR–12/09
SRAM LPC Configuration
Address Latch Requirements
Timing
Multiplexing Data with Address Byte 0
Figure 24-5. Multiplexed SRAM connection using ALE1 and ALE2
The Address Latch timing and parameter requirements are described in
277.
SRAM or external memory devices may have different timing requirements. To meet these vary-
ing requirements, each Chip Select can be configured with different wait-states. Timing details is
described in
The SRAM Low Pin Count (LPC) configuration enables EBI to be configured for multiplexing
modes where the data and address lines are multiplexed. Compared to SRAM configuration,
this can further reduce the number of pins required for the EBI. The available configurations is
shown in
Timing and Address Latch requirements is as for SRAM configuration.
When the data byte and address byte 0 (AD[7:0]) are multiplexed, they are output from the same
port, and the ALE1 signal from the device controls the address latch.
Figure 24-6. Multiplexed SRAM LPC connection using ALE1
Section 24.7.1 on page 272
”EBI Timing” on page
EBI
EBI
A[23:16]/
A[19:16]
A[15:8]/
AD[7:0]
A[15:8]
D[7:0]
A[7:0]
ALE1
ALE2
ALE1
277.
through
D
G
Q
Section 24.7.2 on page
D
G
D
G
Q
Q
D[7:0]
A[7:0]
A[15:8]
A[23:16]
D[7:0]
A[7:0]
A[15:8]
A[19:16]
273.
SRAM
SRAM
”EBI Timing” on page
XMEGA A
272
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