AT91SAM7X256B-AU Atmel, AT91SAM7X256B-AU Datasheet - Page 370
AT91SAM7X256B-AU
Manufacturer Part Number
AT91SAM7X256B-AU
Description
IC MCU 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7X256B-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
64KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
64KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7X256B-AU
Manufacturer:
Atmel
Quantity:
1 800
Part Number:
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Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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• CKG: Receive Clock Gating Selection
• START: Receive Start Selection
• STOP: Receive Stop Selection
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
6120H–ATARM–17-Feb-09
0x9-0xF
START
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
CKG
0x0
0x1
0x2
0x3
Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
Transmit start
Detection of a low level on RF signal
Detection of a high level on RF signal
Detection of a falling edge on RF signal
Detection of a rising edge on RF signal
Detection of any level change on RF signal
Detection of any edge on RF signal
Compare 0
Reserved
Receive Start
None, continuous clock
Receive Clock enabled only if RF Low
Receive Clock enabled only if RF High
Reserved
Receive Clock Gating
AT91SAM7X512/256/128 Preliminary
370
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