ATMEGA1280-16AUR Atmel, ATMEGA1280-16AUR Datasheet - Page 174

• Manufacturer Part Number: ATMEGA1280-16AUR
• Description: MCU AVR 128K FLASH 16MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1280-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
19.1
2549M–AVR–09/10
Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
•
•
•
•
•
•
•
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-12. For the actual
placement of I/O pins, see
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the
The Power Reduction Timer/Counter2 bit, PRTIM2, in
page 56
Figure 19-1. 8-bit Timer/Counter Block Diagram
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
Status flags
must be written to zero to enable Timer/Counter2 module.
Timer/Counter
TCCRnA
OCRnA
TCNTn
“Register Description” on page
OCRnB
=
=
Direction
“Pin Configurations” on page
Count
Clear
ASSRn
Synchronized Status flags
ATmega640/1280/1281/2560/2561
Control Logic
TOP
=
TCCRnB
asynchronous mode
Value
BOTTOM
Fixed
TOP
select (ASn)
clk
=
Tn
0
187.
Prescaler
Synchronization Unit
“PRR0 – Power Reduction Register 0” on
2. CPU accessible I/O Registers, includ-
OCnA
(Int.Req.)
OCnB
(Int.Req.)
Generation
Generation
Waveform
Waveform
TOVn
(Int.Req.)
OCnA
OCnB
Oscillator
T/C
clk
I/O
clk
clk
I/O
ASY
TOSC1
TOSC2
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