ATMEGA325A-MU Atmel, ATMEGA325A-MU Datasheet - Page 40

• Manufacturer Part Number: ATMEGA325A-MU
• Description: IC MCU AVR 32K FLASH 64VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4
9.5
9.6
40
Idle Mode
ADC Noise Reduction Mode
Power-down Mode
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
tion is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is
automatically enabled again. This ensures safe operation in case the VCC level has dropped
during the sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60
µs to ensure that the BOD is working correctly before the MCU continues executing code. BOD
disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see
MCU Control Register” on page
modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active, i.e. BODS
set to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see
MCU Control Register” on page
Note:
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, USI, Timer/Coun-
ters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts
clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI
start condition detection, Timer/Counter2, and the Watchdog to continue operating (if enabled).
This sleep mode basically halts clk
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, USI start condition interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready inter-
rupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from
ADC Noise Reduction mode.
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the
USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter-
nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level
interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically
halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
CPU
and clk
1. BOD disable only available in picoPower devices ATmega165PA/325PA/3250PA/645P/6450P.
FLASH
, while allowing the other clocks to run.
61.
61. Writing this bit to one turns off the BOD in relevant sleep
I/O
, clk
CPU
, and clk
FLASH
, while allowing the other clocks to run.
”External Interrupts” on page 62
8285B–AVR–03/11
”MCUCR –
”MCUCR –