ATMEGA325A-MU Atmel, ATMEGA325A-MU Datasheet - Page 106

• Manufacturer Part Number: ATMEGA325A-MU
• Description: IC MCU AVR 32K FLASH 64VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

106
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 14-3.
Table 14-4
mode.
Table 14-4.
Note:
Table 14-5
rect PWM mode.
Table 14-5.
Note:
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
COM0A1
COM0A1
COM0A1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at BOTTOM. See
page 100
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
pare match is ignored, but the set or clear is done at TOP. See
page 101
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COM0A0
COM0A0
COM0A0
for more details.
for more details.
0
1
0
1
0
1
0
1
0
1
0
1
Table 14-3
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on compare match
Clear OC0A on compare match
Set OC0A on compare match
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match, set OC0A at BOTTOM
(non-inverting mode)
Set OC0A on compare match, clear OC0A at BOTTOM
(inverting mode)
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match when up-counting. Set OC0A on
compare match when down counting.
Set OC0A on compare match when up-counting. Clear OC0A on
compare match when down counting.
shows the COM0A1:0 bit functionality when the WGM01:0 bits
(1)
(1)
”Phase Correct PWM Mode” on
”Fast PWM Mode” on
8285B–AVR–03/11