ATMEGA325A-MU Atmel, ATMEGA325A-MU Datasheet - Page 109

• Manufacturer Part Number: ATMEGA325A-MU
• Description: IC MCU AVR 32K FLASH 64VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15. 16-bit Timer/Counter1
15.1
15.2
8285B–AVR–03/11
Features
Overview
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. Most register and bit references in this sec-
tion are written in general form. A lower case “n” replaces the Timer/Counter number, and a
lower case “x” replaces the Output Compare unit number. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing
Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
p l a c e m e n t o f I / O p i n s , r e f e r t o
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P” on
page
device-specific I/O Register and bit locations are listed in the
130.
The PRTIM1 bit in
enable Timer/Counter1 module
True 16-bit Design (i.e., Allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
”PRR – Power Reduction Register” on page 45
” 6 4 A ( T Q F P ) a n d 6 4 M 1 ( Q F N / M L F ) P i n o u t
”Register Description” on page
Figure
must be written to zero to
15-1. For the actual
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