ATMEGA325A-MU Atmel, ATMEGA325A-MU Datasheet - Page 152

• Manufacturer Part Number: ATMEGA325A-MU
• Description: IC MCU AVR 32K FLASH 64VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
• During asynchronous operation, the synchronization of the Interrupt Flags for the
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following
SLEEP.
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock
(clk
until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-
save mode is essentially unpredictable, as it depends on the wake-up time. The recommended
procedure for reading TCNT2 is thus as follows:
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting of
the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock.
a. Write any value to either of the registers OCR2A or TCCR2A.
b. Wait for the corresponding Update Busy Flag to be cleared.
c. Read TCNT2.
I/O
) again becomes active, TCNT2 will read as the previous value (before entering sleep)
8285B–AVR–03/11