ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 240

• Manufacturer Part Number: ATXMEGA16A4-CU
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• Processor Series: ATXMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 5
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.4
8077H–AVR–12/09
Frame Formats
Leading edge is the first clock edge in a clock cycle. Trailing edge is the last clock edge in a
clock cycle.
Figure 21-4. UCPHA and INVEN data transfer timing diagrams.
Data transfer is frame based, where a serial frame consists of one character of data bits with
synchronization bits (start and stop bits), and an optional parity bit for error checking. Note that
this does not apply to SPI operation (See
The USART accepts all 30 combinations of the following as valid frame formats:
A frame starts with the start bit followed by the least significant data bit and all data bits ending
with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the first
stop bit. One frame can be directly followed by a start bit and a new frame, or the communication
line can return to idle (high) state.
of the frame formats. Bits inside brackets are optional.
Figure 21-5. Frame Formats
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
(IDLE)
St
0
INVEN=0
1
2
Figure 21-5 on page 240
3
4
Section 21.4.2 ”SPI Frame Formats” on page
FRAME
[5]
[6]
[7]
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
[8]
illustrates the possible combinations
[P]
Sp1 [Sp2]
INVEN=1
(St / IDLE)
XMEGA A
241).
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