ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 281
ATXMEGA16A4-CU
Manufacturer Part Number
ATXMEGA16A4-CU
Description
MCU AVR 16+4KB FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA16A4-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATXMEGA16x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
34
Number Of Timers
5
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 12-bit
On-chip Dac
2-ch x 12-bit
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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24.11.3
24.11.4
24.11.5
8077H–AVR–12/09
REFRESH - SDRAM Refresh Period Register
INITDLY - SDRAM Initialization Delay Register
SDRAMCTRLB - SDRAM Control Register B
• Bit 15:10 - Reserved
These bits are reserved and will always be read as zero.
• Bit 9:0 - REFRESH[9:0]: SDRAM Refresh Period
This register sets the refresh period as a number of Peripheral 2x clock (CLK
EBI is busy with another external memory access at time of refresh, up to 4 refresh will be
remembered and given at the first available time.
• Bit 15:14 - Reserved
These bits are reserved and will always be read as zero.
• Bit 13:0 - INITDLY[13:0]: SDRAM Initialization Delay
This register is used to delay the initialisation sequence after the controller is enabled until all
voltages are stabilized and the SDRAM clock has been running long enough to take the SDRAM
chip through its initialisation sequence. The initialisation sequence includes pre-charge all banks
to their idle state issuing an auto-refresh cycle and then loading the mode register. The setting in
this register is as a number of Peripheral 2x clock cycles.
Bit
+0x04
+0x05
Read/Write
Initial Value
Bit
+0x06
+0x07
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
R/W
R/W
R/W
15
15
R
R
7
0
0
7
0
0
7
0
-
-
MRDLY[1:0]
R/W
R/W
R/W
14
14
R
R
6
0
0
6
0
0
6
0
-
-
R/W
R/W
R/W
R/W
13
13
R
5
0
5
0
0
5
0
0
-
ROWCYCDLY[2:0]
R/W
R/W
R/W
R/W
12
12
R
4
0
4
0
0
4
0
0
REFRESH[7:0]
-
INITDLY[7:0]
R/W
R/W
R/W
R/W
11
11
R
3
0
3
0
0
3
0
0
-
INITDLY[9:8]
R/W
R/W
R/W
R/W
10
10
R
2
0
2
0
0
2
0
0
-
RPDLY[2:0]
R/W
R/W
R/W
R/W
R/W
REFRESH[9:8]
1
0
1
9
0
0
1
9
0
0
R/W
R/W
R/W
R/W
R/W
0
0
0
8
0
0
0
8
0
0
XMEGA A
PER
) cycles. If the
SDRAMCTRLB
REFRESHL
REFRESHH
INITDLYL
INITDLYH
281
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