ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 320
ATXMEGA16A4-CU
Manufacturer Part Number
ATXMEGA16A4-CU
Description
MCU AVR 16+4KB FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA16A4-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATXMEGA16x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
34
Number Of Timers
5
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 12-bit
On-chip Dac
2-ch x 12-bit
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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26.10 Register Description
26.10.1
26.10.2
8077H–AVR–12/09
CTRLA – DAC Control Register A
CTRLB – DAC Control Register B
The calibration of the DAC adjust the offset and gain. To calibrate offset you can output mid
code and adjust the offset calibration until you get ~0 LSB offset The gain is adjusted around mid
code so it should not affect the offset calibration if you read the output at mid code and max (or
min code) and adjust the calibration values until you get ~0 LSB gain.
• Bits 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 - IDOEN: DAC Internal Output Enable
Setting this bit routs the internal DAC output to the ADC and Analog Comparator MUXes.
• Bit 3 - CH1EN: DAC Channel 1 Output Enable
Setting this bit will make channel 1 available on pin while clearing the bit makes channel 1 only
available for internal use.
• Bit 2 - CH0EN: DAC Channel 0 Output Enable
Setting this bit will make channel 0 available on pin while clearing the bit makes channel 0 only
available for internal use.
• Bit 1 - Res - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 0 - ENABLE: DAC Enable
This bit enables the entire DAC.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 6:5 - CHSEL[1:0]: DAC Channel Selection
These bits control wether the DAC should operate with single or dual channel outputs.
1
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
shows the available selections.
R
7
0
-
7
R
0
-
R/W
R
6
0
-
6
0
CHSEL[1:0]
R
5
0
-
R
5
0
IDOEN
R/W
4
0
R
4
0
-
CH1EN
R
3
0
R
3
0
-
CH0EN
R/W
2
0
R
2
0
-
CH1TRIG
R/W
R/W
1
0
1
0
.
XMEGA A
CH0TRIG
ENABLE
R/W
R/W
0
0
0
0
Table 26-
CTRLA
CTRLB
320
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