ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 275
ATXMEGA16A4-CU
Manufacturer Part Number
ATXMEGA16A4-CU
Description
MCU AVR 16+4KB FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA16A4-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATXMEGA16x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
34
Number Of Timers
5
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 12-bit
On-chip Dac
2-ch x 12-bit
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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24.8.4
24.8.5
24.8.6
24.9
8077H–AVR–12/09
Combined SRAM & SDRAM Configuration
Timing
Initialization
Refresh
Figure 24-9. 4-Port SDRAM configuration
The Clock Enable (CKE) signal is required for SDRAM when the EBI is clocked at 2x the CPU
clock speed.
Configuring Chip Select 3 to SDRAM will enable the initialization of the SDRAM. The “Load
Mode Register” command is automatically issued at the end of the initialization. For the correct
information to be loaded to the SDRAM, one must do one of the following:
1.
2.
initialized.
The SDRAM initialization is non-interruptible by other EBI accesses.
The EBI will automatically handle the refresh of the SDRAM as long as the refresh period is con-
figured. Refresh will be done as soon as available after the refresh counter reaches the period.
The EBI can collect up to 4 refresh commands in case the interface is busy on another chip
select or in the middle of a read/write at a time a refresh should have been performed.
Combined SRAM and SDRAM configuration enables the EBI to have both SDRAM and SRAM
connected at the same time. This only available for devices with 4 port EBI interface.
10 on page 276
Configure SDRAM control registers before enabling Chip Select 3 to SDRAM.
Issue a “Load Mode Register” command and perform a dummy-access after SDRAM is
EBI
shows the configuration with all interface signals.
CAS/RE
BA[1:0]
CS[3:0]
A[11:8]
A[7:0]]
D[7:0]
DQM
CKE
RAS
CLK
WE
CLK
CKE
BA[1:0]
DQM
WE
RAS
CAS
D[7:0]
A[7:0]
A[11:8]
CS
SDRAM
XMEGA A
Figure 24-
275
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