ATMEGA649P-MUR Atmel, ATMEGA649P-MUR Datasheet - Page 249

• Manufacturer Part Number: ATMEGA649P-MUR
• Description: AVR, 64KB FLASH, 2KB EE, 4KB SRA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649P-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.5.2
8284A–AVR–10/10
LCDCRB – LCD Control and Status Register B
• Bit 0 – LCDBL: LCD Blanking
When this bit is written to one, the display will be blanked after completion of a frame. All seg-
ment and common pins will be driven to ground.
Note:
• Bit 7 – LCDCS: LCD Clock Select
When this bit is written to zero, the system clock is used. When this bit is written to one, the
external asynchronous clock source is used. The asynchronous clock source is either
Timer/Counter Oscillator or external clock, depending on EXCLK in ASSR. See
Operation of Timer/Counter2” on page 158
• Bit 6 – LCD2B: LCD 1/2 Bias Select
When this bit is written to zero, 1/3 bias is used. When this bit is written to one, ½ bias is used.
Refer to the LCD Manufacture for recommended bias selection.
• Bit 5:4 – LCDMUX[1:0]: LCD Mux Select
The LCDMUX[1:0] bits determine the duty cycle. Common pins that are not used are ordinary
port pins. The different duty selections are shown in
Table 23-2.
Note:
• Bits 3:0 – LCDPM[3:0]: LCD Port Mask
The LCDPM3:0 bits determine the number of port pins to be used as segment drivers. The dif-
ferent selections are shown in
port pins.
Table 23-3.
Bit
(0xE5)
Read/Write
Initial Value
LCDPM3
LCDMUX1
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
0
0
0
0
0
1
1
Bit 3, LCDPM3 is only available in ATmega3290A/3290PA/6490A/6490P.
1. 1/2 bias when LCD2B is written to one and 1/3 otherwise.
LCDCS
R/W
LCDPM2
LCD Duty Select
LCD Port Mask (Values in bold are only available in
ATmega3290A/3290PA/6490A/6490P)
7
0
LCDMUX0
0
0
0
0
1
0
1
LCD2B
R/W
6
0
LCDPM1
0
0
1
LCDMUX1
Table 23-3 on page
R/W
5
0
Static
Duty
1/2
1/3
1/4
LCDPM0
LCDMUX0
0
1
0
R/W
for further details.
4
0
1/2 or 1/3
1/2 or 1/3
1/2 or 1/3
Static
Bias
LCDPM3
249. Unused pins can be used as ordinary
R/W
Table 23-2 on page
I/O Port in Use as
Segment Driver
3
0
(1)
(1)
(1)
SEG0:12
SEG0:14
SEG0:16
LCDPM2
COM Pin
R/W
COM0:1
COM0:2
COM0:3
COM0
2
0
LCDPM1
R/W
1
0
249.
Maximum Number
of Segments
LCDPM0
I/O Port Pin
R/W
”Asynchronous
COM1:3
COM2:3
0
0
COM3
None
13
15
17
LCDCRB
249