ATMEGA649P-MUR Atmel, ATMEGA649P-MUR Datasheet - Page 156

• Manufacturer Part Number: ATMEGA649P-MUR
• Description: AVR, 64KB FLASH, 2KB EE, 4KB SRA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649P-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.8
8284A–AVR–10/10
Timer/Counter Timing Diagrams
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2A pin. Setting the COM2A[1:0] bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM2A[1:0] to three (See
162). The actual OC2A value will only be visible on the port pin if the data direction for the port
pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register
at the compare match between OCR2A and TCNT2 when the counter increments, and setting
(or clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the coun-
ter decrements. The PWM frequency for the output when using phase correct PWM can be
calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR2A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set.
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 17-8. Timer/Counter Timing Diagram, no Prescaling
is MAX the OCn pin value is the same as the result of a down-counting compare match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an
up-counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the way
up.
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
Figure 17-8
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
contains timing data for basic Timer/Counter operation. The figure shows the
MAX - 1
Figure 17-7 on page 155
f
OCnxPCPWM
MAX
Figure 17-7 on page
=
----------------- -
N 510
f
clk_I/O
⋅
OCn has a transition from high to low
BOTTOM
155. When the OCR2A value
I/O
should be replaced by
BOTTOM + 1
Table 17-5 on page
156
T2
)