ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 32
![MCU AVR 16K FLASH 4MHZ 36-LGA](/photos/12/32/123221/36ck1-lga_sml.jpg)
ATMEGA16HVA-4CKU
Manufacturer Part Number
ATMEGA16HVA-4CKU
Description
MCU AVR 16K FLASH 4MHZ 36-LGA
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA16HVA-4CKU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
36-LGA
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
Minimum Operating Temperature
- 20 C
On-chip Adc
12 bit, 5 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.13.4
32
ATmega8HVA/16HVA
OSICSR – Oscillator Sampling Interface Control and Status Register
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, or clear the CLK-
PCE bit.
• Bit 1:0 – CLKPS1:0: Clock Prescaler Select Bit 1..0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 9-3 on page
ongoing VADC conversion.
Table 9-3.
Note:
Table 9-4.
Note:
• Bits 7:5,3:2 – RES: Reserved bits
These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero.
Bit
0x17 (0x37)
Read/Write
Initial Value
1. Reserved values should not be written to CLKPS1..0.
1. When changing Prescaler value, the VADC Prescaler will automatically change frequency of
the VADC clock and abort any ongoing conversion.
CLKPS1
CLKPS1
System Clock Prescaler Select
VADC Clock Prescaling
0
0
1
1
0
0
1
1
R
7
–
0
32. Note that writing to the System Clock Prescaler Select bits will abort any
R
6
–
0
R
5
–
0
(1)
OSISEL0
R/W
CLKPS0
CLKPS0
4
0
0
1
0
1
0
1
0
1
R
3
–
0
R
2
–
0
VADC Division Factor
Clock Division Factor
OSIST
R
1
0
Reserved
Reserved
OSIEN
4
2
1
2
4
8
R/W
0
0
8024A–AVR–04/08
(1)
OSICSR
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