ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 28
![MCU AVR 16K FLASH 4MHZ 36-LGA](/photos/12/32/123221/36ck1-lga_sml.jpg)
ATMEGA16HVA-4CKU
Manufacturer Part Number
ATMEGA16HVA-4CKU
Description
MCU AVR 16K FLASH 4MHZ 36-LGA
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA16HVA-4CKU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
36-LGA
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
Minimum Operating Temperature
- 20 C
On-chip Adc
12 bit, 5 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.11
9.12
9.12.1
9.12.2
28
VADC Clock Prescaler
OSI – Oscillator Sampling Interface
ATmega8HVA/16HVA
Features
Overview
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
may be faster than the CPU's clock frequency. It is not possible to determine the state of the
prescaler, and the exact time it takes to switch from one clock division to the other cannot be
exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1
+ 2*T2 before the new clock frequency is active. In this interval, two active clock edges are pro-
duced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new
prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
The VADC clock will be automatically prescaled relative to the System Clock Prescaler settings,
see
CLKPS1..0, the VADC clock, clk
page
•
•
•
•
The Oscillator Sampling Interface (OSI) enables sampling of the Slow RC and Ultra Low Power
RC (ULP) oscillators in ATmega8HVA/16HVA. OSI can be used to calibrate the Fast RC Oscilla-
tor runtime with high accuracy. OSI can also provide an accurate reference for compensating
the ULP Oscillator frequency drift.
The prescaled oscillator phase can be continuously read by the CPU through the OSICSR regis-
ter. In addition, the input capture function of Timer/Counter0 can be set up to trigger on the rising
edge of the prescaled clock. This enables accurate measurements of the oscillator frequencies
relative to the Fast RC Oscillator.
A simplified block diagram of the Oscillator Sampling Interface is shown in
29.
Runtime selectable oscillator input (Slow RC or ULP RC Oscillator)
7 bit prescaling of the selected oscillator
Software read access to the phase of the prescaled clock
Input capture trigger source for Timer/Counter0
CLKPR to zero.
”System Clock Prescaler” on page
32.
VADC
, will be prescaled by 4, 2 or 1 as shown in
27. Depending on the Clock Prescale Select bits,
Figure 9-2 on page
8024A–AVR–04/08
Table 9-4 on
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