ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet
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ATMEGA16HVA-4CKU
Specifications of ATMEGA16HVA-4CKU
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ATMEGA16HVA-4CKU Summary of contents
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... TSOP • Operating Voltage: 1 • Maximum Withstand Voltage (High-voltage pins): 28V • Temperature Range: - 20°C to 85°C • Speed Grade: 1-4 MHz ® 8-bit Microcontroller (1) 8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash ATmega8HVA ATmega16HVA Preliminary 8024A–AVR–04/08 ...
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Pin Configurations 1.1 LGA Figure 1-1. Figure 1- DNC B CF2P C VREF DNC ATmega8HVA/16HVA 2 LGA - Pinout ATmega8HVA/16HVA LGA - pinout ATmega8HVA/16HVA 2 ...
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TSOP Figure 1-3. PV2 PV1 GND VFET CF1P CF1N CF2P CF2N VREG VREF VREFGND 1.3 Pin Descriptions 1.3.1 VFET Input to the internal voltage regulator. 1.3.2 VCC Digital supply voltage. Normally connected to VREG. 1.3.3 VREG Output from the ...
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GND Ground 1.3.8 Port A (PA1..PA0) Port A serves as a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port A pins that are externally pulled low will source current if the ...
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... The chip utilizes Atmel's patented Deep Under-voltage Recovery (DUVR) mode that supports pre-charging of deeply discharged battery cells without using a separate Pre-charge FET. ...
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... CISC microcontrollers. The device is manufactured using Atmel’s high voltage high density non-volatile memory tech- nology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, through an SPI serial interface conventional non-volatile memory programmer On- chip Boot program running on the AVR core ...
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... Comparison Between ATmega8HVA and ATmega16HVA The ATmega8HVA and ATmega16HVA differ only in memory size and interrupt vector size. Table 2-1 Table 2-1. 3. Disclaimer All Min, Typ and Max values contained in this datasheet are preliminary estimates based on sim- ulations and characterization of other AVR microcontrollers manufactured on the same process technology ...
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AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three ...
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SREG – AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Figure 7-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.5 Stack Pointer The Stack is mainly used for storing ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 7-4 vard architecture and the fast-access Register ...
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...
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AVR Memories 8.1 Overview This section describes the different memories in the ATmega8HVA/16HVA. The AVR architec- ture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8HVA/16HVA features an EEPROM Memory for ...
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Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 768 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data ...
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Figure 8-3. 8.4 EEPROM Data Memory The ATmega8HVA/16HVA contains 256 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...
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I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega8HVA/16HVA is a complex microcontroller with more peripheral units than can be ...
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Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines ...
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EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware ...
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Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r17) in address register out EEAR, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to ...
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Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 8.6.4 GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 8.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write ...
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System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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Coulomb Counter ADC Clock - clk The Coulomb Counter ADC is provided with a dedicated clock domain. This allows operating the Coulomb Counter ADC in low power modes like Power-save for continuous current measurements. 9.1.6 Watchdog Timer and Battery ...
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... T is the die temperature in Kelvin and T nature row. The parameter "Slow RC period" holds information about the actual Slow RC oscillator period measured at Atmel production. This parameter can be read from the signature address space. Using the formula above, the actual Slow RC frequency can be found with an error of < ...
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Watchdog Timer, Battery Protection and Coulomb Counter ADC Clock The clock source for the Watchdog Timer, Battery Protection and Coulomb Counter ADC (CC- ADC) is the Ultra Low Power RC Oscillator. The Oscillator is automatically enabled in all opera- ...
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The ripple counter that implements the prescaler runs at the frequency of the undivided clock, may be faster than the CPU's clock frequency not possible to determine the state of the prescaler, and the exact time it takes ...
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Figure 9-2. Note: The osi_posedge signal pulses on each rising edge of the prescaled Slow RC/ ULP oscillator clock. This signal is not directly accessible by the CPU, but can be used to trigger the input cap- ture function of ...
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OSI module. Hence, the calibration algorithm may use the time between the first and second osi_posedge as time reference for calculations. Another usage of OSI is determining the ULP frequency accurately. The ULP frequency at T ...
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The FCAL[4:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x1F gives the highest frequency in the range. Incrementing FCAL[4: ...
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Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written ...
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Bit 4 - OSISEL0: Oscillator Sampling Interface Select 0 Table 9-5. • Bit 1 – OSIST: Oscillator Sampling Interface Status This bit continuously displays the phase of the prescaled clock. This bit can be polled by the CPU to ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Figure 10-1. Sleep Mode State Diagram Sleep Interrupt ADC NRM Black-out Detection Table 10-2. Active modules in different Sleep Modes Module RCOSC_FAST RCOSC_ULP RCOSC_SLOW CPU Flash Timer/Counter n SPI V-ADC CC-ADC External Interrupts CBP 8024A–AVR–04/08 Reset From all States Except ...
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Table 10-2. Active modules in different Sleep Modes (Continued) Module WDT VREG (1) CHARGER_DETECT VREGMON OSI Notes: 1. Discharge FET must be switched off for Charger Detect to be enabled. 2. RCOSC_FAST runs in Power-save mode if DUVR mode is ...
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Note that if a level triggered interrupt is used for wake-up from Power-save mode, the changed level must be held for some time to wake up the MCU. Refer to for details. When waking up from Power-save mode, there is ...
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For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V input buffers can be disabled by writing to the Digital Input Disable Register. Refer to Digital Input Disable Register ...
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Register Description 10.8.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in ...
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Bit 3 - PRSPI: Power Reduction Serial Peripheral Interface Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be reinitialized ...
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System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 11-1. Reset Logic V BATT RESET /dW 11.2.1 Power-on Reset and Charger Connect The Voltage Regulator will not start up until the Charger Detect module has enabled the Voltage Regulator. Before this happens the chip will be in Power-off ...
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Figure 11-2. Normal Start-up Sequence in Power-off. 1. The charger voltage pulls the BATT pin above the Power-on Threshold Voltage (V 2. When V VREG starts to rise. The POR reset will go high while VREG is rising and initiate ...
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When the internal reset goes low, software starts up and loads the VREF calibration reg- isters to get VREF = 1.100V. As the VREF voltage changes, VREG voltage and VFET DUVR voltage will rise proportionally to VREF. Now the ...
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The BOD is automatically enabled in all modes of operation, except in Power-off mode. When the BOD is enabled, and V ure 11-5), the Brown-out Reset is immediately activated. When V level (V expired. Figure 11-5. Brown-out Reset During Operation ...
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Watchdog Timer 11.3.1 Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from • Possible Hardware fuse Watchdog always ...
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In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...
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Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...
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Register Description 11.4.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved ...
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Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog ...
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Table 11-2. WDP3 Note: 8024A–AVR–04/08 Watchdog Timer Prescale Select WDP2 WDP1 WDP0 ...
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Interrupts 12.1 Overview ...
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Addres Label Code s s 0x0000 rjmp 0x0001 rjmp 0x0002 rjmp 0x0003 rjmp 0x0004 rjmp 0x0005 rjmp 0x0006 rjmp 0x0007 rjmp 0x0008 rjmp 0x0009 rjmp 0x000A rjmp 0x000B rjmp 0x000C rjmp 0x000D rjmp 0x000E rjmp 0X000F rjmp 0x0010 rjmp 0x0011 ...
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... Interrupt Vectors in ATmega16HVA . Table 12-2. Vector No the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. ATmega8HVA/16HVA 54 Reset and Interrupt Vectors Program Address Source 0x0000 RESET 0x0002 BPINT 0x0004 VREGMON ...
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... The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16HVA is: Addres Label Code s s 0x0000 jmp 0x0002 jmp 0x0004 jmp 0x0006 jmp 0x0008 jmp 0x000A jmp 0x000C jmp 0x000E jmp 0x0010 jmp 0x0012 jmp 0x0014 jmp ...
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External Interrupts 13.1 Overview The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 pins are configured as outputs. This feature provides a way of gen- erating a ...
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Table 13-1. ISCn1 Note: 13.2.2 EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bits 7:3 – RES: Reserved Bits These bits are reserved bits ins the ATmega8HVA/16HVA, and will always read ...
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High Voltage I/O Ports 14.1 Overview All high voltage AVR ports have true Read-Modify-Write functionality when used as general dig- ital I/O ports. This means that the state of one port pin can be changed without unintentionally changing the ...
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High Voltage Ports as General Digital I/O 14.3 Overview The high voltage ports are high voltage tolerant open collector output ports. In addition they can be used as general digital inputs. pin, here generically called Pxn. Figure 14-2. General ...
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Alternate Port Functions The High Voltage I/O has alternate port functions in addition to being general digital I/O. 14-3 shows how the port pin control signals from the simplified overridden by alternate functions. Figure 14-3. High Voltage Digital I/O ...
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Table 14-1. Signal Name PVOE PVOV DIEOE DIEOV DI 14.4.1 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 14-2. Port Pin The alternate pin configuration is as follows: • INT0 - Port ...
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Register Description 14.5.1 PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 14.5.2 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial Value ATmega8HVA/16HVA – – – – ...
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Low Voltage I/O-Ports 15.1 Overview All low voltage AVR ports have true Read-Modify-Write functionality when used as general digi- tal I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 15.2 Low Voltage Ports as General Digital I/O The low voltage ports ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 15-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS SYNC LATCH Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and ...
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Assembly Code Example C Code Example unsigned char i; Note: 15.2.5 Digital Input Enable and Sleep Modes As shown in input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-save ...
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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...
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Note: Table 15-2 ure 15-5 on page 68 generated internally in the modules having the alternate function. Table 15-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions ...
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Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 15-3. The alternate pin configuration is as follows: • ADC0/ SNGD/ T0 – Port A, Bit 0 Voltage Analog to Digital Converter (Channel ...
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Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 15-5. Port Pin PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • MISO/INT2 - Port B, Bit 3 MISO, Master ...
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Table 15-6. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB3/MISO PUOE SPE • MSTR PUOV PORTB3 • PUD DDOE SPE • MSTR DDOV 0 PVOE SPE • MSTR PVOV SPI SLAVE OUTPUT PTOE – DIEOE INT2 ENABLE DIEOV ...
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Register Description 15.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the ...
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Timer/Counter0 and Timer/Counter1 Prescalers 16.1 Overview Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1.1 Internal Clock Source The Timer/Counter can be ...
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External Clock Source An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro- nized (sampled) signal is ...
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Register Description 16.3.1 TCCRnB – Timer/Counter n Control Register B Bit Read/Write Initial Value • Bits – CSn2, CSn1, CSn0: Clock Select n, Bit 2, 1, and 0 The Clock Select n bits 2, 1, and ...
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Timer/Counter(T/C0,T/C1) 17.1 Features • Clear Timer on Compare Match (Auto Reload) • Input Capture unit • Four Independent Interrupt Sources (TOVn, OCFnA, OCFnB, ICFn) • 8-bit Mode with Two Independent Output Compare Units • 16-bit Mode with One Independent ...
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Registers The Timer/Counter Low Byte Register (TCNTnL) and Output Compare Registers (OCRnA and OCRnB) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked ...
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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 17-2 on page 79 Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count clk Tn top The counter is incremented at each ...
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Modes of Operation The mode of operation is defined by the Timer/Counter Width (TCWn), Input Capture Enable (ICENn) and the Waveform Generation Mode (WGMn0)bits in Control Register A” on page Table 17-2. Modes of Operation Mode ICENn TCWn WGMn0 ...
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Figure 17-3. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCFnA Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the ...
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Input Capture Mode The Timer/Counter can be used in a 8-bit Input Capture mode, see settings. For full description, see 17.5.6 16-bit Input Capture Mode The Timer/Counter can also be used in a 16-bit Input Capture mode, see ...
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When a change of the logic level (an event) occurs on the Input Capture pin (ICPx), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the value of ...
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I/O bit location). For measuring frequency only, the trigger edge change is not required. Table 17-3. ICS0 0 1 Note: 1. See Table 17-4. ICS1 0 1 17.7 Output Compare Unit ...
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Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNTnH/L Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnB ...
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Figure 17-8. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx shows the setting of OCFnA and the clearing of TCNTn in CTC mode. Figure 17-9. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f ...
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The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnB/A registers. Assembly Code Example C Code Example Note: The ...
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The following code examples show how atomic read of the TCNTn register contents. Reading any of the OCRn register can be done by using the same principle. Assembly Code Example TIMn_ReadTCNTn: ; Save global interrupt flag in ...
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The following code examples show how atomic write of the TCNTnH/L register con- tents. Writing any of the OCRnB/A registers can be done by using the same principle. Assembly Code Example TIMn_WriteTCNTn: C Code Example void TIMn_WriteTCNTn( ...
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Register Description 17.10.1 TCCRnA – Timer/Counter n Control Register A Bit Read/Write Initial Value • Bit 7– TCWn: Timer/Counter Width When this bit is written to one 16-bit mode is selected. The Timer/Counter width is set to 16-bits and ...
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TCNTnL – Timer/Counter n Register Low Byte Bit Read/Write Initial Value The Timer/Counter Register TCNTnL gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNTnL Register blocks (disables) the Com- ...
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OCRnB – Timer/Counter n Output Compare Register B Bit Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNTnL in 8-bit mode and TCNTnH in 16-bit mode). A ...
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TIFRn – Timer/Counter n Interrupt Flag Register Bit Read/Write Initial Value • Bits 3 – ICFn: Timer/Counter n Input Capture Flag This flag is set when a capture event occurs, according to the setting of ICENn, ICESn and ICSn ...
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SPI – Serial Peripheral Interface 18.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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Table 18-1. Pin MOSI MISO SCK SS Note: 1. See The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual ...
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Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8024A–AVR–04/08 (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi out ; Enable SPI ldi out ret SPI_SlaveReceive: ...
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SS Pin Functionality 18.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 ATmega8HVA/16HVA 100 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE ...
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Register Description 18.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...
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Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...
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SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...
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Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC 19.1 Features • Sampled System Coulomb Counter • Low Power Sigma-Delta ADC Optimized for Coulomb Counting • Instantaneous Current Output with 3.9 ms Conversion Time – 13 bit Resolution (including sign ...
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The Accumulate Current Output provides a highly accurate current measure- ment for Coulomb Counting. The CC-ADC also provides a special Regular Current detection mode. This allows ultra-low power operation in Power-save mode when small charge or discharge ...
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Figure 19-3. Accumulation Current Conversions Enable Accumulation Interrupt Accumulation Data Read byte 1 Read byte 2 Read byte 3 Read byte 4 19.4 Regular Current Detection Operation By setting the CADSE bit in CADCSRA the CC-ADC will enter a special ...
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Instantaneous Current Interrupt should be enabled as wake-up source by setting the CADICIE bit. The device will then wake-up from sleep after each single IC measurement. To check if Reg- ular Current Detection has occurred the Regular Current Detection flag, ...
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Bit 5 - CADUB: CC-ADC Update Busy The CC-ADC operates in a different clock domain than the CPU. Whenever a new value is writ- ten to CADCSRA or CADRC this value must be synchronized to the CCADC clock domain. ...
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CADCSRB - CC-ADC Control and Status Register B Bit (0xE5) Read/Write Initial Value • Bits 7 - Res: Reserved This bit is reserved bit and will always read as zero. • Bit 6 - CADACIE: CC-ADC Accumulate Current Interrupt ...
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CADICH and CADICL - CC-ADC Instantaneous Current Bit (0xE9) (0xE8) Read/Write Initial Value When a CC-ADC Instantaneous Current conversion is complete, the result is found in these two registers. CADIC[15:0] represents the converted result in 2's complement format. CADIC[12:0] ...
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CADRC- CC-ADC Regular Current Bit (0xE6) Read/Write Initial Value The CC-ADC Regular Current Register determines the threshold level for the Regular Current detection. When the result of a CC-ADC Instantaneous Current conversion has an absolute value greater than, or ...
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Voltage ADC – 5-channel General Purpose 12-bit Sigma-Delta ADC 20.1 Features • 12-bit Resolution • 519µs Conversion Time @ 1 MHz clk • Two Differential Input Channels for Cell Voltage Measurements • Three Single Ended Input Channels • 0.2x ...
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Power-off mode. Note that the bandgap voltage reference must be enabled and disabled sepa- rately, see Figure 20-2. Voltage ADC Conversion Diagram Start Conversion Interrupt Conversion Result To perform a V-ADC conversion, the analog input channel must first be selected ...
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Register Description 20.4.1 VADMUX – V-ADC Multiplexer Selection Register Bit (0x7C) Read/Write Initial Value • Bit 7:4 – RES: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. • Bit 3:0 – ...
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VADSC will read as one as long as the conversion is not finished. When the conversion is com- plete, it returns to zero. Writing zero to this bit has no effect. VADSC will automatically be cleared when the VADEN bit ...
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DIDR0 – Digital Input Disable Register 0 Bit (0x7E) Read/Write Initial Value • Bits 7:2 – Res: Reserved Bits These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to zero ...
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... V-ADC and CC-ADC. To guarantee ultra low temperature drift after factory calibration, ATmega8HVA/16HVA features a two-step calibration algorithm. The first step is performed at T temperature. By default, Atmel factory calibration is performed the signature row. The value of T Signature Row from Software” on page 144 second calibration step in their test flow ...
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Figure 21-1. Reference Circuitry 21.3 Register Description 21.3.1 BGCCR – Bandgap Calibration C Register Bit (0xD0) Read/Write Initial Value • Bit 7 - BGD: Bandgap Disable Setting the BGD bit to one will disable the bandgap voltage reference. This bit ...
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BGCRR – Bandgap Calibration R Register Bit (0xD1) Read/Write Initial Value • Bit 7:0 – BGCR7:0: BG Calibration of Resistor ladder These bits are used for temperature gradient adjustment of the bandgap reference. illustrates VREF as a function of ...
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Voltage Regulator 22.1 Features • 3.3V fixed output voltage • Automatic selection of Step-up or Linear Regulation depending on VFET voltage. • Fixed Linear Regulation mode can be selected for 2-cell applications • Battery Pack Short mode allowing large ...
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Figure 22-1. Voltage regulator block diagram, combined Step-up and Linear mode VFET BATT Figure 22-2. Voltage regulator operation and reset signals as a function of rising and falling Regulator operation DUVR mode Power-on Reset 8024A–AVR–04/08 Voltage Regulator VIN VREF VREF ...
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Figure 22-3. Voltage Regulator block diagram, Linear mode only VFET BATT Figure 22-4. Voltage regulator operation and reset signals as a function of rising and falling Regulator operation DUVR mode Power-on Reset Chip Reset ATmega8HVA/16HVA 122 Voltage Regulator VIN VREF ...
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Voltage Regulator Monitor This module monitors the operating state of the Voltage Regulator. If the voltage at VFET drops below the Regulator Short-circuit Level (RSCL), see Voltage Regulator enters the Battery Pack Short mode. In this mode, VFET is ...
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Battery Protection 23.1 Features • Short-circuit Protection • Discharge Over-current Protection • Charge Over-current Protection • Discharge High-current Protection • Charge High-current Protection • Programmable and Lockable Detection Levels and Reaction Times • Autonomous Operation Independent of CPU 23.2 ...
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The Current Battery Protection (CBP) monitors the cell current by sampling the shunt resistor voltage at the PI/NI input pins. A differential operational amplifier amplifies the voltage with a suitable gain. The output from the operational amplifier is compared to ...
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When the Discharge High-current Protection is activated, the external D-FET and C-FET are dis- abled and a Current Protection Timer is started. This timer ensures that the FETs are disabled for at least one second. The application software must then ...
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CPU. This interrupt can wake up the CPU from any operation mode, except Power-off. The interrupt flags are cleared by writing a logic ‘1’ to their bit locations from the CPU. Note that there are ...
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Bit 4 – SCD: Short Circuit Protection Disabled When the SCD bit is set, the Short-circuit Protection is disabled. The Short-circuit Detection will be disabled, and any Short-circuit condition will be ignored. • Bit 3 – DOCD: Discharge Over-current ...
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Table 23-2. Notes: Note: 23.9.4 BPOCTR – Battery Protection Over-current Timing Register Bit (0xFB) Read/Write Initial Value • Bit 7:6 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 5:0 – OCPT5:0: Over-current ...
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Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator cycles + 3 CPU clock cycles is required between each time the BPOCTR register is written. Any writing to the BPOCTR register during this ...
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BPSCD – Battery Protection Short-circuit Detection Level Register Bit (0xF5) Read/Write Initial Value • Bits 7:0 – SCDL7:0: Short-circuit Detection Level These bits sets the R as defined in Note: 23.9.7 BPDOCD – Battery Protection Discharge-Over-current Detection Level Register ...
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BPDHCD – Battery Protection Discharge-High-current Detection Level Register Bit (0xF8) Read/Write Initial Value • Bits 7:0 – DHCDL7:0: Discharge High-current Detection Level These bits sets the R Table 23-5 on page Note: Due to synchronization of parameters between clock ...
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Table 23-5. All other values 23.9.11 BPIMSK – Battery Protection Interrupt Mask Register Bit (0xF2) Read/Write Initial Value • Bit 7:5 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 4 – SCIE: ...
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Bit 0 - CHCIE : Charger High-current Protection Activated Interrupt The CHCIE bit enables interrupt caused by the Charge High-current Protection Activated Interrupt. 23.9.12 BPIFR – Battery Protection Interrupt Flag Register Bit (0xF3) Read/Write Initial Value • Bit 7:5 ...
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FET Control 24.1 Overview The FET control is used to enable and disable the Charge FET and Discharge FET. Normally, the FETs are enabled and disabled by SW writing to the FET Control and Status Register (FCSR). However, the ...
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FET Driver 24.2.1 Features • Charge-pump for generating suitable gate drive for N-Channel FET switch on high side • Deep Under-voltage Recovery mode that allows normal operation while charging a Deeply Over- discharged battery from 0-volt 24.2.2 Overview The ...
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Figure 24-3. Switching NFET on and off during NORMAL operation 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 24.3 DUVR – Deep Under-Voltage Recovery Mode operation The purpose of DUVR mode is to control ...
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Register Description 24.4.1 FCSR – FET Control and Status Register Bit (0xF0) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero. • Bit 3 ...
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On-chip Debug System 25.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...
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When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. ...
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Self-Programming the Flash 26.1 Overview The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) ...
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Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page ...
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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...
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A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if ...
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Table 26-1. Signature Byte Description Reserved BGCCR Calibration Byte @ HOT V-ADC RAW Cell1 L V-ADC RAW Cell1 H V-ADC RAW ADC0 L V-ADC RAW ADC0 H VPTAT CAL L VPTAT CAL H V-ADC Cell1 Calibration Word L V-ADC Cell1 ...
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... Explanation of different variables used in pointer, ATmega8HVA. Corresponding Z-value 11 5 Z12 Z6 PC[11:6] Z12:Z7 PC[5:0] Z6:Z1 Explanation of different variables used in pointer, ATmega16HVA. Corresponding Z-value 12 Table 26-2 shows the typical program- (1) = 8.0 MHz Max Programming Time 3.7 ms 4.5 ms Figure 26-1 and the mapping to the Z- Description Most significant bit in the Program Counter ...
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... An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending the Z-pointer) into the destina- tion register. See 8024A–AVR–04/08 Explanation of different variables used in pointer, ATmega16HVA. Corresponding Z-value Description Most significant bit which is used to address the ...
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Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The ...
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Memory Programming 27.1 Program And Data Memory Lock Bits The ATmega8HVA/16HVA provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in be erased to “1” with the ...
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High Byte Table 27-3. Bit No 7 Note: 1. The default OSCSEL1:0 setting should not be changed. OSCSEL1:0 = ‘00’ is reserved for test 27.2.2 Low Byte Table 27-4. Bit ...
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... Page Size Table 27-6. No. of Words in a Page and No. of Pages in the Flash, ATmega8HVA/16HVA Device Flash Size ATmega8HVA 4K words (8K bytes) ATmega16HVA 8K words (16K bytes) Table 27-7. No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size 256 bytes 27.6 Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND ...
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Figure 27-1. Serial Programming and Verify. Table 27-8. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The ...
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The serial programming instructions will not work if the communication is out of synchro- nization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is ...
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... Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use word address. This address may be random within the page range. 7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. ATmega8HVA/16HVA ...
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If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded ...
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High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data mem- ory, Lock bits and Fuse bits in the ATmega8HVA/16HVA. Figure 27-3. High-voltage Serial Programming Table 27-11. Pin Name Mapping Signal Name in ...
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High-voltage Serial Programming Algorithm To program and verify the ATmega8HVA/16HVA in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in 27.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in Serial ...
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Chip Erase The Chip Erase will erase the Flash and EEPROM not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are ...
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Figure 27-5. High-voltage Serial Programming Waveforms SDI SII SDO SCI 27.8.5 Programming the EEPROM The EEPROM is organized in pages, see When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to ...
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Table 27-14. High-voltage Serial Programming Instruction Set for ATmega8HVA/16HVA Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load “Write Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_ bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page ...
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Table 27-14. High-voltage Serial Programming Instruction Set for ATmega8HVA/16HVA (Continued) Instruction Instr.1/5 SDI 0_bbbb_bbbb_00 Read EEPROM SII 0_0000_1100_00 Byte SDO x_xxxx_xxxx_xx SDI 0_0100_0000_00 Write Fuse High SII 0_0100_1100_00 Byte SDO x_xxxx_xxxx_xx SDI 0_0100_0000_00 Write Fuse Low SII 0_0100_1100_00 Byte SDO ...
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Operating Circuit Figure 28-1. Operating Circuit Diagram, 2-cell. Notes: 1. The series resistors on the SPI lines are required for In-System Programming and On-chip 2. PA1 should be connected to SGND when measuring V( recommended to ...
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Figure 28-2. Operating Circuit Diagram, 1-cell Notes: 8024A–AVR–04/08 Rcf VFET PV2 470 RP PV1 470 CP 0.1uF RP NV 470 Rpi PI 100 Rsense ATmega8HVA/16HVA Ci 0.010 0.1uF Rni NI 100 PA1/ADC1/SGND PA0/ADC0/SGND RT2 RT1 R1 10K ...
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Table 28-1. Recommended values for external devices Symbol Use R1 Pull-up resistor for thermistors RT1/RT2 NTC Thermistor Source impedance when using R S PA1..PA0 as V-ADC inputs CREF VREF decoupling CREG VREG charge-storage capacitor CVCC VCC decoupling capacitor CF1 Fly ...
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Electrical Characteristics 29.1 Absolute Maximum Ratings* Operating Temperature.................................... -20°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on PA0 - PA1, PI, and NI with respect to Ground ............................. -0. Voltage on PB0 - PB3 with ...
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DC Characteristics Table 29-1. Electrical Characteristics Parameter Active Idle ADC Noise Reduction Supply Current Power-save Power-off ATmega8HVA/16HVA 166 ( -10°C to 70°C unless otherwise specified) A Condition 4.0 MHz, 4V ≤ V ≤ 8.4V, FET All PRR ...
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Table 29-1. Electrical Characteristics Parameter Voltage Regulator Operating Voltage Regulated Output Voltage (V ) REG Voltage (2) Regulator V Linear/Step-up FET (5) switching level Voltage Regulator Short-circuit Level (RSCL) Ripple, Step-up mode Reference Voltage VREF Ref. Voltage Accuracy (3)(5) Temperature ...
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... After scaling of VADC raw data using Gain and Offset Calibration values stored in Signature Row. 8. Actual offset for each channel stored in signature row can be used to remove this offset error the cell input needs to be measured when PV1 is below 1.5V, Atmel can provide data that facilitates less accurate mea- surements in this range. ...
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General I/O Lines characteristics (1) Table 29- -10°C to 70° Symbol Parameter Input Low Voltage, Except V IL RESET pin Input Low Voltage, V IL1 RESET pin Input High Voltage Except RESET pin ...
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FET Driver Characteristics Table 29-5. FET Driver Outputs specification Parameter Condition 1 cell DUVR operation, VREF = 1.100V (2) VFET DC level 2 cell DUVR operation, VREF = 1.100V 1 cell DUVR operation (2) VFET ripple 2 cell DUVR ...
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SPI Timing Characteristics See Figure 29-1 on page 171 and Table 29-7. SPI Timing Parameters Description 1 SCK period 2 SCK high/low 3 Rise/Fall time 4 Setup 5 Hold 6 Out to SCK 7 SCK to out 8 SCK ...
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SPI Interface Timing Requirements (Slave Mode) (CPOL = 0) (CPOL = 1) (Data Input) (Data Output) 29.8 Programming Characteristics 29.8.1 Serial Programming Figure 29-2. Serial Programming Timing Figure 29-3. Serial Programming Waveforms SERIAL DATA INPUT SERIAL DATA OUTPUT SERIAL CLOCK ...
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Table 29-8. Serial Programming Characteristics, T Symbol Parameter 1/t Oscillator Frequency (ATmega8HVA/16HVA) CLCL t Oscillator Period (ATmega8HVA/16HVA) CLCL t SCK Pulse Width High SHSL t SCK Pulse Width Low SLSH t MOSI Setup to SCK High OVSH t MOSI Hold ...
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Typical Characteristics – Preliminary Data All Typical Characteristics contained in this data sheet are based on simulation and character- ization of other AVR microcontrollers manufactured in the same process technology. These figures are preliminary and will be updated after ...
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Register Summary Address Name Bit 7 (0xFF) Reserved – (0xFE) BPPLR – (0xFD) BPCR – (0xFC) BPHCTR – (0xFB) BPOCTR – (0xFA) BPSCTR – (0xF9) BPCHCD (0xF8) BPDHCD (0xF7) BPCOCD (0xF6) BPDOCD (0xF5) BPSCD (0xF4) Reserved – (0xF3) BPIFR ...
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Address Name Bit 7 (0xBF) Reserved – (0xBE) Reserved – (0xBD) Reserved – (0xBC) Reserved – (0xBB) Reserved – (0xBA) Reserved – (0xB9) Reserved – (0xB8) Reserved – (0xB7) Reserved – (0xB6) Reserved – (0xB5) Reserved – (0xB4) Reserved – ...
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Address Name Bit 7 (0x7D) Reserved – (0x7C) VADMUX – (0x7B) Reserved – (0x7A) VADCSR – (0x79) VADCH – (0x78) VADCL (0x77) Reserved – (0x76) Reserved – (0x75) Reserved – (0x74) Reserved – (0x73) Reserved – (0x72) Reserved – (0x71) ...
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Address Name Bit 7 0x1B (0x3B) Reserved – 0x1A (0x3A) Reserved – 0x19 (0x39) Reserved – 0x18 (0x38) Reserved – 0x17 (0x37) OSICSR – 0x16 (0x36) TIFR1 – 0x15 (0x35) TIFR0 – 0x14 (0x34) Reserved – 0x13 (0x33) Reserved – ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Instruction Set Summary (Continued) Mnemonics Operands BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register LSL Rd Logical ...
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... NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break Note: 1. These instructions are only available in ATmega16HVA. 8024A–AVR–04/08 Description P ← Rr STACK ← ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega8HVA/16HVA ...
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Ordering Information 33.1 ATmega8HVA Speed (MHz) Power Supply 1.8 - 9.0V Notes: 1. Pb-free packaging, complies with the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 36CK1 36-pad, (6.50 ...
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... Body, 0.60 mm Pitch), Land Grid Array (LGA) Package. 28T 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) 8024A–AVR–04/08 ATmega8HVA/16HVA Ordering Code Package ATmega16HVA-4CKU 36CK1 ATmega16HVA-4TU 28T Package Type (1) Operation Range -20 to +85°C ...
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Packaging Information 34.1 36CK1 Marked Bottom View Notes: 1. This drawing is for general information only. 2. Metal pad dimensions > Dummy pad. TITLE 2325 Orchard Parkway 36CK1, ...
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Pin 1 Identifier Area e E Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and ...
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... Errata 35.1 ATmega8HVA 35.1.1 Rev known errata. 35.2 ATmega16HVA 35.2.1 Rev known errata. ATmega8HVA/16HVA 186 8024A–AVR–04/08 ...
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Datasheet Revision History 36.1 Rev. 8024A – 04/08 1. 8024A–AVR–04/08 Initial revision ATmega8HVA/16HVA 187 ...
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ATmega8HVA/16HVA 188 8024A–AVR–04/08 ...
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... Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1LGA ...........................................................................................................................2 1.2TSOP .........................................................................................................................3 1.3Pin Descriptions .........................................................................................................3 2 Overview ................................................................................................... 5 2.1Comparison Between ATmega8HVA and ATmega16HVA .......................................7 3 Disclaimer ................................................................................................. 7 4 Resources ................................................................................................. 7 5 Data Retention .......................................................................................... 7 6 About Code Examples ............................................................................. 7 7 AVR CPU Core .......................................................................................... 8 7.1Overview ....................................................................................................................8 7.2ALU – Arithmetic Logic Unit .......................................................................................9 7.3Status Register ..........................................................................................................9 7.4General Purpose Register File ................................................................................11 7 ...
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... System Control and Reset .................................................................... 41 11.1Resetting the AVR .................................................................................................41 11.2Reset Sources .......................................................................................................41 11.3Watchdog Timer ....................................................................................................46 11.4Register Description ..............................................................................................49 12 Interrupts ................................................................................................ 52 12.1Overview ................................................................................................................52 12.2Interrupt Vectors in ATmega8HVA ........................................................................52 12.3Interrupt Vectors in ATmega16HVA ......................................................................54 13 External Interrupts ................................................................................. 56 13.1Overview ................................................................................................................56 13.2Register Description ..............................................................................................56 14 High Voltage I/O Ports ........................................................................... 58 14.1Overview ................................................................................................................58 14.2High Voltage Ports as General Digital I/O .............................................................59 14.3Overview ................................................................................................................59 ...
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Port Functions ........................................................................................60 14.5Register Description ..............................................................................................62 15 Low Voltage I/O-Ports ............................................................................ 63 15.1Overview ................................................................................................................63 15.2Low Voltage Ports as General Digital I/O ..............................................................64 15.3Alternate Port Functions ........................................................................................68 15.4Register Description ..............................................................................................73 16 Timer/Counter0 and Timer/Counter1 Prescalers ................................ 74 16.1Overview ................................................................................................................74 16.2External ...
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Usage .....................................................................................107 19.7Register Description ............................................................................................107 20 Voltage ADC – 5-channel General Purpose 12-bit Sigma-Delta ADC 112 20.1Features ..............................................................................................................112 20.2Overview ..............................................................................................................112 20.3Operation .............................................................................................................112 20.4Register Description ............................................................................................114 21 Voltage Reference and Temperature Sensor .................................... 117 21.1Features ..............................................................................................................117 21.2Overview ..............................................................................................................117 21.3Register ...
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... I/O Lines characteristics ........................................................................169 29.5FET Driver Characteristics ..................................................................................170 29.6Power-on and Reset Characteristics ...................................................................170 29.7SPI Timing Characteristics ..................................................................................171 29.8Programming Characteristics ..............................................................................172 30 Typical Characteristics – Preliminary Data ....................................... 174 31 Register Summary ............................................................................... 175 32 Instruction Set Summary ..................................................................... 179 33 Ordering Information ........................................................................... 182 33.1ATmega8HVA ......................................................................................................182 33.2ATmega16HVA ....................................................................................................183 8024A–AVR–04/08 ATmega8HVA/16HVA v ...
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... Packaging Information ........................................................................ 184 34.136CK1 ..................................................................................................................184 34.228T ......................................................................................................................185 35 Errata ..................................................................................................... 186 35.1ATmega8HVA ......................................................................................................186 35.2ATmega16HVA ....................................................................................................186 36 Datasheet Revision History ................................................................. 187 36.1Rev. 8024A – 04/08 .............................................................................................187 Table of Contents....................................................................................... i ATmega8HVA/16HVA vi 8024A–AVR–04/08 ...
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ATmega8HVA/16HVA vii ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...