ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 130
ATMEGA16HVA-4CKU
Manufacturer Part Number
ATMEGA16HVA-4CKU
Description
MCU AVR 16K FLASH 4MHZ 36-LGA
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA16HVA-4CKU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
36-LGA
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
Minimum Operating Temperature
- 20 C
On-chip Adc
12 bit, 5 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.9.5
130
ATmega8HVA/16HVA
BPHCTR – Battery Protection High-current Timing Register
Note:
• Bit 7:6 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 5:0 – HCPT5:0: High-current Protection Timing
These bits control the delay of the High-circuit Protection. The High-current Timing can be set
with a step size of 2 ms as shown in
Table 23-4.
Notes:
Note:
Bit
(0xFC)
Read/Write
Initial Value
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPOCTR register is written. Any
writing to the BPOCTR register during this period will be ignored.
1. The actual value depends on the actual frequency of the
2. Initial value.
3. An additional delay T
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPHCTR register is written. Any
writing to the BPHCTR register during this period will be ignored.
applies when enabling the Discharge FET. For Charge Over-Current protection, this applies
when enabling the Charge FET. With nominal ULP frequency this delay is maximum 0.1 ms.
page
the initialization of the protection circuitry. For the Discharge High-Current protection, this
applies when enabling the Discharge FET. For Charge High-Current protection, this applies
when enabling the Charge FET. With nominal ULP frequency this delay is maximum 0.2 ms.
High-current Protection Reaction Time. HCPT[5:0] with corresponding High-cur-
rent Delay Time.
26. See
R
7
–
0
HCPT[5:0]
0x01
0x3E
0x00
0x02
0x03
0x3F
...
”Electrical Characteristics” on page
(2)
R
6
–
0
High-current Protection Reaction Time
d
can be expected after enabling the corresponding FET. This is related to
R/W
5
0
Table 23-4 on page
R/W
4
0
R/W
3
0
HCPT[5:0]
165.
130.
R/W
(122 - 124 ms) + T
(124 - 126 ms) + T
2
0
”Ultra Low Power RC Oscillator” on
(0 - 2 ms) + T
(0 - 2 ms) + T
(2 - 4 ms) + T
(4 - 6 ms) + T
(1)
R/W
Typ
...
1
0
d
d
d
d
(3)
(3)
(3)
(3)
d
d
R/W
(3)
(3)
0
1
8024A–AVR–04/08
BPHCTR
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