PIC18F65K22-I/MRRSL Microchip Technology, PIC18F65K22-I/MRRSL Datasheet - Page 425

• Manufacturer Part Number: PIC18F65K22-I/MRRSL
• Description: MCU PIC 32K FLASH MEM XLP 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K22-I/MRRSL

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC18
• No. Of I/o's: 53
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 28-4:
28.6.1
The program memory may be read to, or written from,
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPx bits have no direct
effect. CPx bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTx Configuration bit is ‘ 0 ’.
The EBTRx bits control table reads. For a block of user
memory, with the EBTRx bit set to ‘ 0 ’, a table read
instruction that executes from within that block is allowed
to read. A table read instruction that executes from a
FIGURE 28-7:
 2010 Microchip Technology Inc.
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
30000Bh CONFIG6H
30000Ch CONFIG7L EBTR7
30000Dh CONFIG7H
Legend: Shaded cells are unimplemented.
Note 1:
File Name
Results: All table writes disabled to Blockn whenever WRTx = 0
TBLPTR = 0008FFh
Register Values
This bit is available only on the PIC18F67K22 and PIC18F87K22 devices.
PROGRAM MEMORY
CODE PROTECTION
PC = 00BFFEh
PC = 003FFEh
SUMMARY OF CODE PROTECTION REGISTERS
TABLE WRITE (WRTx) DISALLOWED
WRT7
CP7
WRTD
Bit 7
CPD
—
(1)
(1)
(1)
EBTR6
WRT6
EBTRB
CP6
WRTB
Bit 6
CPB
(1)
(1)
(1)
EBTR5
WRT5
Program Memory
WRTC
CP5
Bit 5
Preliminary
—
—
(1)
TBLWT*
TBLWT*
(1)
(1)
EBTR4
WRT4
CP4
PIC18F87K22 FAMILY
Bit 4
—
—
—
location outside of that block is not allowed to read and
will result in reading ‘ 0 ’s. Figures 28-7 through 28-9
illustrate table write and table read protection.
(1)
(1)
Note:
(1)
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
.
EBTR3
WRT3
Bit 3
CP3
—
—
—
Code protection bits may only be written to
a ‘ 0 ’ from a ‘ 1 ’ state. It is not possible to
write a ‘ 1 ’ to a bit in the ‘ 0 ’ state. Code
protection bits are only set to ‘ 1 ’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
programming
information.
Configuration Bit Settings
EBTR2
WRT2
Bit 2
CP2
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
—
—
—
Refer
specification
EBTR1
WRT1
Bit 1
CP1
—
—
—
DS39960B-page 425
to
the
for
EBTR0
WRT0
Bit 0
CP0
device
—
—
—
more