PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 89

• Manufacturer Part Number: PIC18LF1330-I/SO
• Description: IC PIC MCU FLASH 4KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF1330-I/SO

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No.: RoHS Compliant
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 10-2:
 2009 Microchip Technology Inc.
PORTA
LATA
TRISA
INTCON
INTCON2
ADCON1
CMCON
CVRCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
Name
RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
TRISA7
GIE/GIEH PEIE/GIEL
LATA7
CVREN
C2OUT
RA7
RBPU
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
—
(1)
(1)
(1)
TRISA6
INTEDG0
LATA6
C1OUT
RA6
Bit 6
—
—
(1)
(1)
(1)
PORTA Output Latch Register (Read and Write to Data Latch)
PORTA Data Direction Control Register
INTEDG1 INTEDG2 INTEDG3
TMR0IE
C0OUT
CVRR
Bit 5
RA5
—
CVRSS
VCFG0
INT0IE
Bit 4
RA4
—
PCFG3
CVR3
RBIE
Bit 3
RA3
—
PIC18F1230/1330
TMR0IF
TMR0IP
CMEN2
PCFG2
CVR2
Bit 2
RA2
CMEN1
PCFG1
INT0IF
INT3IP
CVR1
Bit 1
RA1
CMEN0
PCFG0
CVR0
RBIF
RBIP
Bit 0
RA0
DS39758D-page 89
on Page:
Values
Reset
50
49
49
47
47
48
48
48