PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 200

• Manufacturer Part Number: PIC18LF1330-I/SO
• Description: IC PIC MCU FLASH 4KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF1330-I/SO

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No.: RoHS Compliant
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F1230/1330
REGISTER 20-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
REGISTER 20-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
DS39758D-page 200
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5-0
Note 1:
U-0
U-0
—
—
It is recommended to enable the corresponding CPx bit to protect block from external read operations.
It is recommended to enable the corresponding CPx bit to protect block from external read operations.
Unimplemented: Read as ‘0’
EBTR1: Table Read Protection bit (Block 1 Code Memory Area)
1 = Block 1 is not protected from table reads executed in other blocks
0 = Block 1 is protected from table reads executed in other blocks
EBTR0: Table Read Protection bit (Block 0 Code Memory Area)
1 = Block 0 is not protected from table reads executed in other blocks
0 = Block 0 is protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
EBTRB: Table Read Protection bit (Boot Block Memory Area)
1 = Boot Block is not protected from table reads executed in other blocks
0 = Boot Block is protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
EBTRB
R/C-1
U-0
—
(1)
C = Clearable bit
C = Clearable bit
U-0
U-0
—
—
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U-0
U-0
—
—
U-0
U-0
—
—
 2009 Microchip Technology Inc.
EBTR1
R/C-1
U-0
—
(1)
EBTR0
R/C-1
U-0
—
bit 0
bit 0
(1)