PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet

IC PIC MCU FLASH 4KX16 18SOIC

PIC18LF1330-I/SO

Manufacturer Part Number
PIC18LF1330-I/SO
Description
IC PIC MCU FLASH 4KX16 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF1330-I/SO

Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No.
RoHS Compliant
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1330-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS39758C), the following
clarifications and corrections should be noted. Any
silicon issues related to the PIC18F1230/1330 will be
reported in a separate silicon errata. Please check the
Microchip web site for any existing issues.
1. Module: Oscillator Configurations – PLL
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation. If PLL is
enabled and a Two-Speed Start-up from wake is
performed, execution is delayed until the PLL
starts.
FIGURE 6-3:
© 2008 Microchip Technology Inc.
The second paragraph of Section 2.6.4 “PLL in
INTOSC Modes”, is modified by the addition of
new text shown in bold.
21
TBLPTRU
TABLE POINTER BOUNDARIES BASED ON OPERATION
PIC18F1230/1330 Data Sheet Errata
16
15
TABLE ERASE
TBLPTR<21:6>
PIC18F1230/1330
TBLPTRH
TBLPTR<21:3>
TABLE WRITE
2. Module: Flash Program Memory
When the timed write to program memory begins (via
the WR bit), the 19 MSbs of the TBLPTR
(TBLPTR<21:3>) determine which program memory
block of 8 bytes is written to. The Table Pointer
register’s three LSBs (TBLPTR<2:0>) are ignored.
For more detail, see Section 6.5 “Writing to Flash
Program Memory”.
In Section 6.2.4 “Table Pointer Boundaries”,
the third paragraph and Figure 6-3 are modified:
• The paragraph is modified by the removal of the
• Figure 6-3 is modified as shown.
TABLE READ – TBLPTR<21:0>
first sentence and the addition of new text
shown in bold.
8
7
TBLPTRL
DS80352B-page 1
0

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PIC18LF1330-I/SO Summary of contents

Page 1

... FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU © 2008 Microchip Technology Inc. PIC18F1230/1330 2. Module: Flash Program Memory In Section 6.2.4 “Table Pointer Boundaries”, the third paragraph and Figure 6-3 are modified: • The paragraph is modified by the removal of the first sentence and the addition of new text shown in bold ...

Page 2

... RXDTP has no effect on the Synchronous mode DT signal. The register table and new bit descriptions appear as shown. R/W-0 R/W-0 U-0 TXCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2008 Microchip Technology Inc. ...

Page 3

... Service Routine is modified with the new text shown in bold. a) End the mismatch condition by doing either of the following: - Reading or writing to CMCON - Returning the input to its original state b) Clear flag bit CMPxIF © 2008 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R/W-0 VCFG0 PCFG3 PCFG2 U = Unimplemented bit, read as ‘0’ ...

Page 4

... Table 17-1 and REF VOLTAGE REFERENCE OUTPUT C Comparator Input VREF Disabled No reference 0 Disabled From V 1 REF (CV bypassed) REF Enabled From CV 0 REF Enabled From CV 1 REF R/W-0 R/W-0 R/W-0 CVR2 CVR1 CVR0 bit Bit is unknown ) SS © 2008 Microchip Technology Inc. ...

Page 5

... FIGURE 17-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = REF AV DD CVRSS = 0 CVREN CVRR AV SS © 2008 Microchip Technology Inc. PIC18F1230/1330 8R CVR3:CVR0 Steps CVRSS = x CVREN = 0 CV REF CVREN = 1 DS80352B-page 5 ...

Page 6

... STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled DS80352B-page 6 Register 19-6, R/P-0 U-0 BBSIZ0 — Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 U-0 R/P-1 — — STVREN bit 0 © 2008 Microchip Technology Inc. ...

Page 7

... PIC18F1230/1330 devices These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify part number. Note 1: The values for DEV10:DEV3 may be shared with other devices. A device can be identified by using the entire, DEV10:DEV0 bit sequence. © 2008 Microchip Technology Inc. PIC18F1230/1330 ...

Page 8

... E/W -40°C to +85°C V Using EECON to read/write V = Minimum operating MIN voltage ms Year Provided no other specifications are violated E/W -40°C to +85°C mA E/W -40°C to +85° Minimum operating MIN voltage Minimum operating MIN voltage ms Year Provided no other specifications are violated mA © 2008 Microchip Technology Inc. ...

Page 9

... Initial release of this data sheet errata. Includes Data Sheet Clarifications 1 (Oscillator Configurations – PLL), 2 (Flash Program Memory), 3 (EUSART), 4 (A/D), 5 (Comparator), 6 (Comparator Voltage Reference), 7 (Special Features of the CPU) and 8 (Electrical Characteristics). Rev B Document (9/2008) Changes to Data Sheet Clarification 7 (Special Features of the CPU). © 2008 Microchip Technology Inc. PIC18F1230/1330 DS80352B-page 9 ...

Page 10

... PIC18F1230/1330 NOTES: DS80352B-page 10 © 2008 Microchip Technology Inc. ...

Page 11

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 12

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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