PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 39

• Manufacturer Part Number: PIC18LF1330-I/SO
• Description: IC PIC MCU FLASH 4KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF1330-I/SO

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No.: RoHS Compliant
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.0
The PIC18F1230/1330 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 20.2 “Watchdog
Timer (WDT)”.
FIGURE 5-1:
 2009 Microchip Technology Inc.
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
OSC1
MCLR
V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
2: See Table 5-2 for time-out situations.
RESET
Instruction
INTRC
RESET
OST/PWRT
Pointer
32 s
Stack
( )_IDLE
Brown-out
Time-out
V
(1)
Detect
DD
WDT
Reset
Sleep
Rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-Bit Ripple Counter
11-Bit Ripple Counter
POR Pulse
BOREN
1024 Cycles
65.5 ms
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
5.1
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 5.6 “Reset State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 11.0 “Interrupts”. BOR is covered in
Section 5.4 “Brown-out Reset (BOR)”.
RCON Register
PIC18F1230/1330
S
R
DS39758D-page 39
Q
Enable OST
Enable PWRT
Chip_Reset
(2)