ATMEGA8535-16PU Atmel, ATMEGA8535-16PU Datasheet - Page 68

• Manufacturer Part Number: ATMEGA8535-16PU
• Description: IC AVR MCU 8K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: SPI/TWI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 8K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCU Control and Status
Register – MCUCSR
General Interrupt Control
Register – GICR
68
ATmega8535(L)
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 36. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
Table 36. Interrupt 0 Sense Control
• Bit 6 – ISC2: Interrupt Sense Control 2
The asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG
I-bit and the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a
falling edge on INT2 activates the interrupt. If ISC2 is written to one, a rising edge on
INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on
INT2 wider than the minimum pulse width given in Table 37 will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2
bit, an interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing
its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally,
the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit
(INTF2) in the GIFR Register before the interrupt is re-enabled.
Table 37. Asynchronous External Interrupt Characteristics
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU General Control Register (MCUCR) define whether the external
interrupt is activated on the rising and/or falling edge of the INT1 pin or level sensed.
Activity on the pin will cause an interrupt request even if INT1 is configured as an output.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Symbol
ISC01
t
INT
0
0
1
1
Parameter
Minimum pulse width for asynchronous external
interrupt
ISC00
R/W
0
1
0
1
INT1
R/W
7
–
0
7
0
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
ISC2
R/W
INT0
R/W
6
0
6
0
INT2
R/W
R
5
–
0
5
0
R/W
4
–
R
4
–
0
WDRF
R/W
3
R
3
–
0
See Bit Description
BORF
R/W
2
R
2
–
0
Min
EXTRF
IVSEL
R/W
R/W
1
1
0
Typ
50
PORF
IVCE
R/W
R/W
0
Max
2502G–AVR–04/05
0
0
MCUCSR
GICR
Units
ns