ATMEGA8535-16PU Atmel, ATMEGA8535-16PU Datasheet
ATMEGA8535-16PU
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ATMEGA8535-16PU Summary of contents
Page 1
... PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega8535L – 4.5 - 5.5V for ATmega8535 • Speed Grades – MHz for ATmega8535L – MHz for ATmega8535 ® 8-bit Microcontroller 8-bit Microcontroller with 8K Bytes In-System Programmable ...
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... Pin Configurations Disclaimer ATmega8535(L) 2 Figure 1. Pinout ATmega8535 (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 (MOSI) PB5 1 33 PA4 (ADC4) (MISO) PB6 ...
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... Overview Block Diagram 2502G–AVR–04/05 The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega8535 AVR is supported with a full suite of program and system develop- ment tools including: C compilers, macro assemblers, program debugger/simulators, In- Circuit Emulators, and evaluation kits. ...
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... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega8535 as listed on page 59. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... About Code Examples ATmega8535(L) 6 This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit defini- tions in the header files and interrupt handling compiler dependent ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. ATmega8535(L) 8-bit Data Bus Status and Control ...
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... ALU – Arithmetic Logic Unit ATmega8535(L) 8 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash pro- gram memory ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc- tion Set Description” for detailed information. ATmega8535( ...
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... General Purpose Register File ATmega8535(L) 10 The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • ...
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... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit SP7 SP6 SP5 Read/Write R/W R/W R/W R/W R/W R/W Initial Value ATmega8535( R26 (0x1A R28 (0x1C R30 (0x1E SP9 SP4 SP3 SP2 SP1 4 ...
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... Instruction Execution Timing Reset and Interrupt Handling ATmega8535(L) 12 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept ...
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... EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega8535(L) 13 ...
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... Interrupt Response Time ATmega8535(L) 14 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set global interrupt enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8535 Program Counter (PC bits wide, thus addressing the 4K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 512 bytes of inter- nal data SRAM in the ATmega8535 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. ...
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... Data RD Memory Access Instruction The ATmega8535 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. “ ...
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... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega8535 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. • ...
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... The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU. Table 1. EEPROM Programming Time Symbol EEPROM Write (from CPU) Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings. ATmega8535(L) Number of Calibrated (1) RC Oscillator Cycles Programming Time 8448 Typ 8 ...
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... ATmega8535(L) 20 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter- rupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM com- mand to finish ...
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... EEPROM and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. ATmega8535(L) 21 ...
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... The I/O space definition of the ATmega8535 is shown in page 297. All ATmega8535 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchronously when clk tion in all sleep modes. The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. ATmega8535(L) ADC CPU Core RAM clk ...
Page 24
... The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscil- lator is voltage dependent as shown in “ATmega8535 Typical Characteristics – Preliminary Data” on page 264. Table 3. Number of Watchdog Oscillator Cycles Typ Time-out ( ...
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... Notes: 1. The frequency ranges are preliminary values. 2. This option should not be used with crystals, only with ceramic resonators. ATmega8535(L) XTAL2 XTAL1 GND (1) Recommended Range for Capacitors (MHz) C1 and C2 for Use with Crystals (pF) – ...
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... ATmega8535(L) 26 The CKSEL0 fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. Table 5. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and CKSEL0 SUT1..0 Power-save 0 00 258 258 16K 16K 16K CK Notes: 1. These options should only be used when not operating close to the maximum fre- quency of the device, and only if frequency stability at start-up is not important for the application ...
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... Figure 13. External RC Configuration The Oscillator can operate in four different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 7. ATmega8535(L) Additional Delay from Reset (V = 5.0V) Recommended Usage CC 4.1 ms Fast rising power or BOD enabled ...
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... Calibrated Internal RC Oscillator ATmega8535(L) 28 Table 7. External RC Oscillator Operating Modes CKSEL3..0 0101 0110 0111 1000 When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 8. Table 8. Start-up Times for the External RC Oscillator Clock Selection Start-up Time from Power-down and SUT1 ...
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... Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 11. Table 11. Internal RC Oscillator Frequency Range. Min Frequency in Percentage of OSCCAL Value Nominal Frequency (%) 0x00 0x7F 0xFF 100 ATmega8535(L) Additional Delay from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4.1 ms Fast rising power ...
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... External Clock Timer/Counter Oscillator ATmega8535( drive the device from an external clock source, XTAL1 should be driven as shown in Figure 14. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND ...
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... If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 11 on page 23 presents the different clock systems in the ATmega8535, and their distribution. The figure is helpful in selecting an appropriate sleep mode. The MCU Control Register contains control bits for power management. ...
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... ADC Noise Reduction Mode Power-down Mode Power-save Mode ATmega8535(L) 32 When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two- wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating ...
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... From Extended Standby mode, the device wakes up in six clock cycles. Oscillators Main Clock Timer Source Osc clk clk Enabled Enabled IO ADC ASY ( ( ATmega8535(L) , allowing operation only of asyn- ASY Wake up sources INT2 TWI INT1 Address Timer EEPROM INT0 Match 2 Ready ( ( (2) (3) (2) X ...
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... Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins ATmega8535(L) 34 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as possible of the device’s functions are operating ...
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... The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 24. The ATmega8535 has four sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...
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... ATmega8535(L) 36 Figure 15. Reset Logic Power-on Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL Pull-up Resistor Spike Reset Circuit Filter Watchdog Timer Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] Table 15. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold (2) Voltage (falling) ...
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... This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega8535L and BODLEVEL = 0 for ATmega8535. BODLEVEL = 1 is not applicable for ATmega8535. A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 15 ...
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... MCU after the Time-out period t Figure 18. External Reset During Operation CC ATmega8535 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed ...
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... To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. ATmega8535( – ...
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... Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8535 resets and executes from the Reset Vector. For tim- ing details on the Watchdog Reset, refer to page 39. ...
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... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega8535 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... ATmega8535( the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow- ing procedure must be followed the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. ...
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... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret C Code Example void WDT_off(void Reset WDT */ _WDR() /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } ATmega8535(L) 43 ...
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... Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 ATmega8535(L) 44 The sequence for changing the Watchdog Timer configuration differs slightly between the three safety levels. Separate procedures are described for each level. This mode is compatible with the Watchdog operation found in AT90S8535. The Watch- dog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction ...
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... Interrupts Interrupt Vectors in ATmega8535 2502G–AVR–04/05 This section describes the specifics of the interrupt handling as performed in ATmega8535. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 19. Reset and Interrupt Vectors Vector Program (2) No. Address Source ...
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... Note: 1. The Boot Reset Address is shown in Table 93 on page 233. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega8535 is: AddressLabels Code 0x000 ...
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... SPH,r16 0xC17 ldi r16,low(RAMEND) 0xC18 out SPL,r16 0xC19 sei 0xC20 <instr> xxx ATmega8535(L) Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler Comments ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ...
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... Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR ATmega8535(L) 48 The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit INT1 INT0 INT2 Read/Write R/W R/W R/W Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory ...
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... Enable change of interrupt vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret C Code Example void Move_interrupts(void Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); } ATmega8535(L) 49 ...
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... I/O-Ports Introduction ATmega8535(L) 50 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input) ...
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... If PORTxn is written a logic zero when the pin is configured as an output pin, the port pin is driven low (zero). When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = ATmega8535( DDxn ...
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... Reading the Pin Value ATmega8535(L) 52 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable high-impedant environment will not notice the dif- ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports ...
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... In this case, the delay t clock period. Figure 25. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 ATmega8535(L) and t pd,max pd,min through the synchronizer is one system pd 0xFF nop in r17, PINx 0x00 ...
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... Digital Input Enable and Sleep Modes ATmega8535(L) 54 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins ...
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... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V cause excessive currents if the pin is accidentally configured as an output. ATmega8535(L) or GND is not recommended, since this may CC 55 ...
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... Alternate Port Functions ATmega8535(L) 56 Most port pins have alternate functions in addition to being general digital I/Os. Figure 26 shows how the port pin control signals from the simplified Figure 23 can be overrid- den by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR micro- controller family ...
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... This is the Analog Input/Output to/from alternate functions. The Input/output signal is connected directly to the pad, and can be used bi- directionally. The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega8535(L) 57 ...
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... Special Function IO Register – SFIOR Alternate Functions of Port A ATmega8535(L) 58 Bit ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). ...
Page 59
... Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced by the SPI input, the pull-up can still be con- trolled by the PORTB6 bit. ATmega8535(L) PA2/ADC2 PA1/ADC1 0 ...
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... ATmega8535(L) 60 • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5 ...
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... PC1 SDA (Two-wire Serial Bus Data Input/Output Line) PC0 SCL (Two-wire Serial Bus Clock Line) The alternate pin configuration is as follows: • TOSC2 – Port C, Bit 7 ATmega8535(L) PB5/MOSI PB4/SS SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • ...
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... ATmega8535(L) 62 TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asyn- chronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. ...
Page 63
... ICP1 – Input Capture Pin: The PD6 pin can act as an Input Capture pin for Timer/Counter1. • OC1A – Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output ATmega8535(L) (1) PC0/SCL TWEN PORTC0 • PUD ...
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... ATmega8535(L) 64 (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. • OC1B – Port D, Bit 4 OC1B, Output Compare Match B output: The PD4 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDD4 set (one)) to serve this function ...
Page 65
... Bit PORTB7 PORTB6 PORTB5 Read/Write R/W R/W R/W Initial Value Bit DDB7 DDB6 DDB5 Read/Write R/W R/W R/W Initial Value ATmega8535(L) PD2/INT0 PD1/TXD PD0/RXD 0 TXEN RXEN 0 0 PORTD0 • PUD 0 TXEN RXEN TXEN 0 0 TXD 0 INT0 ENABLE INT0 INPUT – RXD – ...
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... PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND ATmega8535(L) 66 Bit PINB7 PINB6 PINB5 Read/Write R ...
Page 67
... Any logical change on INT1 generates an interrupt request The falling edge of INT1 generates an interrupt request The rising edge of INT1 generates an interrupt request. • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 ATmega8535( SM0 ISC11 ISC10 ISC01 ISC00 R/W ...
Page 68
... MCU Control and Status Register – MCUCSR General Interrupt Control Register – GICR ATmega8535(L) 68 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 36 ...
Page 69
... INT2 interrupt disabled, the input buffer on this pin will be disabled. This may cause a logic change in internal signals which will set the INTF2 Flag. See “Digital Input Enable and Sleep Modes” on page 54 for more information. ATmega8535( ...
Page 70
... Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the actual placement of I/O pins, refer to “Pinout ATmega8535” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
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... Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clk Timer/Counter clock, referred to as clk Tn ATmega8535(L) TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) top in the following ...
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... Output Compare Unit ATmega8535(L) 72 top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk T0 clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped ...
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... The OC0 Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take effect immediately. ATmega8535(L) 73 ...
Page 74
... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega8535(L) 74 The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera- tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 30 shows a simplified schematic of the logic affected by the COM01:0 bit setting ...
Page 75
... An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM ATmega8535(L) OCn Interrupt Flag Set 2 ...
Page 76
... Fast PWM Mode ATmega8535(L) 76 when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the Compare Match ...
Page 77
... This feature is similar to the OC0 toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. ATmega8535(L) OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set ...
Page 78
... Phase Correct PWM Mode ATmega8535(L) 78 The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while up-counting, and set on the Compare Match while down-counting ...
Page 79
... The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 34. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn Figure 35 shows the same timing data, but with the prescaler enabled. ATmega8535(L) f clk_I/O = ----------------- - ⋅ N 510 T0 MAX BOTTOM ) is therefore BOTTOM + 1 79 ...
Page 80
... ATmega8535(L) 80 Figure 35. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 36 shows the setting of OCF0 in all modes except CTC mode. Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode ...
Page 81
... Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn OCFn ATmega8535(L) TOP BOTTOM TOP BOTTOM + 1 81 ...
Page 82
... Timer/Counter Register Description Timer/Counter Control Register – TCCR0 ATmega8535(L) 82 Bit FOC0 WGM00 COM01 Read/Write W R/W R/W Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode ...
Page 83
... Set OC0 on Compare Match when up-counting. Clear OC0 on Compare Match when down-counting. Note special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 78 for more details. ATmega8535(L) (1) (1) 83 ...
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... Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK ATmega8535(L) 84 • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 43. Clock Select Bit Description CS02 ...
Page 85
... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow Interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. ATmega8535( ...
Page 86
... Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega8535(L) 86 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2 ...
Page 87
... The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. ATmega8535(L) < f /2) given a 50/50% duty cycle. Since ExtClk clk_I/O /2 ...
Page 88
... A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the actual placement of I/O pins, refer to “Pinout ATmega8535” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” ...
Page 89
... The output from the Clock Select logic is referred to as the timer clock (clk T The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the ATmega8535(L) (1) TOVn (Int.Req.) Clock Select ...
Page 90
... Definitions Compatibility ATmega8535(L) 90 Waveform Generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 97. The Compare Match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an output compare interrupt request. ...
Page 91
... Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. ATmega8535(L) 91 ...
Page 92
... ATmega8535(L) 92 The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 ...
Page 93
... TCNT1. If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATmega8535(L) 93 ...
Page 94
... Timer/Counter Clock Sources Counter Unit ATmega8535(L) 94 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 86 ...
Page 95
... Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high ATmega8535(L) DATA BUS (8-bit) TCNTnH (8-bit) ...
Page 96
... Input Capture Trigger Source Noise Canceler Using the Input Capture Unit ATmega8535(L) 96 byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’ ...
Page 97
... The OCR1x Register is double buffered when using any of the twelve Pulse Width Mod- ulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting ATmega8535(L) DATA BUS (8-bit) TCNTnH (8-bit) ...
Page 98
... Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit ATmega8535(L) 98 sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not the case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly ...
Page 99
... OC1x Register performed on the next Compare Match. For com- pare output actions in the non-PWM modes refer to Table 45 on page 109. For fast PWM mode refer to Table 46 on page 110, and for phase correct and phase and fre- quency correct PWM refer to Table 47 on page 110. ATmega8535( ...
Page 100
... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega8535(L) 100 A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. ...
Page 101
... PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High fre- ATmega8535(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set ...
Page 102
... ATmega8535(L) 102 quency allows physically small sized external components (coils, capacitors), hence reducing total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM ...
Page 103
... PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or ATmega8535(L) f clk_I/O = ---------------------------------- - ⋅ ...
Page 104
... ATmega8535(L) 104 OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution can be calculated in bits by using the following equation: R PCPWM In phase correct PWM mode, the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11) ...
Page 105
... The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: R PFCPWM ATmega8535(L) f clk_I/O = --------------------------- - ⋅ ...
Page 106
... ATmega8535(L) 106 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direc- tion. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown in Figure 48 ...
Page 107
... OCF1x. Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 50 shows the same timing data, but with the prescaler enabled. ATmega8535(L) f clk_I/O = --------------------------- - ⋅ ⋅ TOP OCRnx OCRnx + 1 OCRnx Value ) is therefore T1 OCRnx + 2 ...
Page 108
... ATmega8535(L) 108 Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 51 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode, the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on ...
Page 109
... COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected Toggle OC1A/OC1B on Compare Match Clear OC1A/OC1B on Compare Match (set output to low level Set OC1A/OC1B on Compare Match (set output to high level). ATmega8535(L) /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 FOC1A FOC1B ...
Page 110
... ATmega8535(L) 110 Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 46. Compare Output Mode, Fast PWM COM1A1/ COM1A0/ COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation) ...
Page 111
... PWM, Phase and Frequency Correct 1 0 PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 Reserved 1 0 Fast PWM 1 1 Fast PWM ATmega8535(L) Update of TOV1 Flag x TOP OCR1 at Set on 0xFFFF Immediate MAX 0x00FF TOP BOTTOM 0x01FF TOP BOTTOM 0x03FF TOP BOTTOM ...
Page 112
... Timer/Counter1 Control Register B – TCCR1B ATmega8535(L) 112 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output ...
Page 113
... The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is per- formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 91. ATmega8535( ...
Page 114
... Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega8535(L) 114 Bit OCIE2 TOIE2 TICIE1 Read/Write R/W R/W R/W Initial Value Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. • ...
Page 115
... TOV1 Flag is set when the timer overflows. Refer to Table 48 on page 111 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega8535( ...
Page 116
... Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the actual placement of I/O pins, refer to “Pinout ATmega8535” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 117
... When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Status Register – ASSR” on page 130. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 133. ATmega8535( default equal to the MCU clock, clk T2 ...
Page 118
... Counter Unit Output Compare Unit ATmega8535(L) 118 The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 54 shows a block diagram of the counter and its surrounding environment. Figure 54. Counter Unit Block Diagram DATA BUS count clear TCNTn Control Logic direction ...
Page 119
... The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the force output compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between Waveform Generation modes. ATmega8535(L) DATA BUS TCNTn = (8-bit Comparator ) OCFn (Int ...
Page 120
... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega8535(L) 120 Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. The Compare Output mode (COM21:0) bits have two functions. The Waveform Genera- tor uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match ...
Page 121
... The timing diagram for the CTC mode is shown in Figure 57. The counter value (TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. Figure 57. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period 1 ATmega8535(L) OCn Interrupt Flag Set (COMn1 121 ...
Page 122
... Fast PWM Mode ATmega8535(L) 122 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOT- TOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature ...
Page 123
... This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. ATmega8535(L) OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set ...
Page 124
... Phase Correct PWM Mode ATmega8535(L) 124 The Phase Correct PWM mode (WGM21 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM ...
Page 125
... PWM mode. Figure 60. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn Figure 61 shows the same timing data, but with the prescaler enabled. ATmega8535(L) f clk_I/O = ----------------- - ⋅ N 510 MAX BOTTOM I/O BOTTOM + 1 125 ...
Page 126
... ATmega8535(L) 126 Figure 61. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 62 shows the setting of OCF2 in all modes except CTC mode. Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 ...
Page 127
... Modes of oper- ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and “Modes of Operation” on page 121. ATmega8535(L) TOP BOTTOM TOP ...
Page 128
... ATmega8535(L) 128 Table 51. Waveform Generation Mode Bit Description WGM21 WGM20 Timer/Counter Mode Mode (CTC2) (PWM2) of Operation Normal PWM, Phase Correct CTC Fast PWM Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def- initions. However, the functionality and location of these bits are compatible with previous versions of the timer. • ...
Page 129
... Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register. ATmega8535(L) (1) Description No clock source (Timer/Counter stopped). ...
Page 130
... Output Compare Register – OCR2 Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR ATmega8535(L) 130 Bit Read/Write R/W R/W R/W Initial Value The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt generate a waveform output on the OC2 pin ...
Page 131
... Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power- ATmega8535(L) 131 ...
Page 132
... Timer/Counter Interrupt Mask Register – TIMSK ATmega8535(L) 132 down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake-up from Power-save or Extended Standby mode when the timer ...
Page 133
... For Timer/Counter2, the possible prescaled selections are: clk clk /128, clk /256, and clk T2S T2S T2S selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. ATmega8535( OCF1A OCF1B TOV1 OCF0 R/W ...
Page 134
... Special Function IO Register – SFIOR ATmega8535(L) 134 Bit ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W Initial Value • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect ...
Page 135
... Serial Peripheral Interface – SPI 2502G–AVR–04/05 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8535 and peripheral devices or between several AVR devices. The ATmega8535 SPI includes the following features: • Full Duplex, Three-wire Synchronous Data Transfer • ...
Page 136
... ATmega8535(L) 136 done, writing a byte to the SPI Data Register starts the SPI Clock Generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener- ator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested ...
Page 137
... DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; } Note: 1. See “About Code Examples” on page 6. ATmega8535(L) 137 ...
Page 138
... ATmega8535(L) 138 The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) ...
Page 139
... When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, MSTR will ATmega8535( ...
Page 140
... ATmega8535(L) 140 be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL func- tionality is summarized below: Table 57 ...
Page 141
... WCOL set, and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega8535 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 59) ...
Page 142
... Data Modes ATmega8535(L) 142 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on oppo- site edges of the SCK signal, ensuring sufficient time for data signals to stabilize ...
Page 143
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: 1. Refer to Figure 1 on page 2, Table 34 on page 65, and Table 28 on page 61 for USART pin placement. ATmega8535(L) (1) Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL ...
Page 144
... AVR USART vs. AVR UART – Compatibility Clock Generation ATmega8535(L) 144 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The clock generation logic consists of synchronization logic for exter- nal clock input used by synchronous slave operation, and the baud rate generator ...
Page 145
... UMSEL, U2X and DDR_XCK bits. Table 61 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. ATmega8535(L) fosc UBRR ...
Page 146
... Double Speed Operation (U2X) External Clock ATmega8535(L) 146 Table 61. Equations for Calculating Baud Rate Register Setting Equation for Calculating Operating Mode Asynchronous Normal Mode (U2X = 0) BAUD Asynchronous Double Speed Mode (U2X = 1) BAUD Synchronous Master Mode BAUD Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps). ...
Page 147
... Figure 72 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 72. Frame Formats (IDLE Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. ATmega8535(L) Sample Sample FRAME 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 147 ...
Page 148
... Parity Bit Calculation USART Initialization ATmega8535(L) 148 Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter ...
Page 149
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine or be combined with initialization code for other I/O modules. ATmega8535(L) 149 ...
Page 150
... Data Transmission – The USART Transmitter Sending Frames with Data Bits ATmega8535(L) 150 The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output ...
Page 151
... Register. For compatibility with future devices, always write this bit to zero when writing the UCSRA Register. When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty interrupt will be executed as long as UDRE is set (pro- vided that global interrupts are enabled). UDRE is cleared by writing UDR. When ATmega8535(L) 151 ...
Page 152
... Parity Generator Disabling the Transmitter ATmega8535(L) 152 interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates ...
Page 153
... Get and return received data from buffer */ return UDR; } Note: 1. See “About Code Examples” on page 6. The function simply waits for data to be present in the receive buffer by checking the RXC Flag, before reading the buffer and returning the value. ATmega8535(L) 153 ...
Page 154
... Receiving Frames with 9 Data Bits ATmega8535(L) 154 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR, and PE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change ...
Page 155
... Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is ATmega8535(L) 155 ...
Page 156
... Asynchronous Data Reception Asynchronous Clock Recovery ATmega8535(L) 156 stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a Parity Error. The PE bit is set if the next character that can be read from the receive buffer had a par- ity error when received and the parity checking was enabled at that point (UPM1 = 1) ...
Page 157
... RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 75 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. ATmega8535(L) START ...
Page 158
... Asynchronous Operational Range ATmega8535(L) 158 Figure 75. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = Sample (U2X = The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set. ...
Page 159
... The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible. ATmega8535(L) Max Total Recommended Max (%) ...
Page 160
... Multi-processor Communication Mode Using MPCM ATmega8535(L) 160 Setting the Multi-processor Communication Mode (MPCM) bit in UCSRA enables a fil- tering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU system with multiple MCUs that communicate via the same serial bus ...
Page 161
... Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1); ... Note: 1. See “About Code Examples” on page 6. As the code examples illustrate, write accesses of the two registers are relatively unaf- fected of the sharing of I/O location. ATmega8535(L) 161 ...
Page 162
... USART Register Description USART I/O Data Register – UDR ATmega8535(L) 162 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents ...
Page 163
... This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. ATmega8535( ...
Page 164
... USART Control and Status Register B – UCSRB ATmega8535(L) 164 • Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from effec- tively doubling the transfer rate for asynchronous communication. • ...
Page 165
... UCSRC. The URSEL must be one when writing the UCSRC. • Bit 6 – UMSEL: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 64. UMSEL Bit Settings UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega8535( UPM0 USBS UCSZ1 UCSZ0 UCPOL ...
Page 166
... ATmega8535(L) 166 • Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmit- ter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and com- pare it to the UPM0 setting ...
Page 167
... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor- rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. ATmega8535(L) Received Data Sampled (Input on RxD Pin) Falling XCK Edge ...
Page 168
... UBRR = 0, Error = 0.0% ATmega8535(L) 168 For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 69. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table ...
Page 169
... ATmega8535( 7.3728 MHz osc U2X = 1 U2X = 0 Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0.8% 31 0.0% 25 ...
Page 170
... Max 0.5 Mbps 1 Mbps 1. UBRR = 0, Error = 0.0% ATmega8535(L) 170 11.0592 f = MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR -0.1% 287 0.0% 575 0.2% 143 0.0% 287 0.2% 71 0.0% 143 0. ...
Page 171
... Mbps 1.152 Mbps ATmega8535( 20.0000 MHz osc U2X = 1 U2X = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0. ...
Page 172
... Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology ATmega8535(L) 172 • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows up to 128 Different Slave Addresses • ...
Page 173
... START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. ATmega8535(L) Data Stable Data Change 173 ...
Page 174
... Address Packet Format Data Packet Format ATmega8535(L) 174 Figure 78. START, REPEATED START, and STOP Conditions SDA SCL START All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation performed, otherwise a write operation should be per- formed ...
Page 175
... Masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process. The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all Masters will be wired-ANDed, yielding a combined clock with a high ATmega8535(L) Data LSB ACK 7 ...
Page 176
... ATmega8535(L) 176 period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively ...
Page 177
... Note that the inter- nal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones. ATmega8535(L) SDA Slew-rate Spike ...
Page 178
... Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit ATmega8535(L) 178 This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres- caler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency ...
Page 179
... Bit 6 – TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is writ- ten to one, the ACK pulse is generated on the TWI bus if the following conditions are met: ATmega8535( ...
Page 180
... ATmega8535(L) 180 1. The device’s own slave address has been received general call has been received, while the TWGCE bit in the TWAR is set data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the Two- wire Serial Bus temporarily ...
Page 181
... TWI logic, the CPU cannot access the ACK bit directly. • Bits 7..0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus. Bit TWA6 TWA5 TWA4 ATmega8535( TWS4 TWS3 – TWPS1 TWPS0 R ...
Page 182
... ATmega8535(L) 182 Read/Write R/W R/W R/W Initial Value The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as slaves by other masters ...
Page 183
... START condition was successfully transmitted. If TWSR indicates other- wise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must ATmega8535(L) 7. Check TWSR to see if data was sent and ACK received. Application loads ...
Page 184
... ATmega8535(L) 184 load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However important that the TWINT bit is set in the value written ...
Page 185
... TWCR = (1<<TWINT) | (1<<TWEN); while (!(TWCR & (1<<TWINT))) ; if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega8535(L) Comments Send START condition. Wait for TWINT Flag set. This indicates that the START condition has been transmitted. Check value of TWI Status Register ...
Page 186
... Transmission Modes ATmega8535(L) 186 The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST), and Slave Receiver (SR). Several of these modes can be used in the same application example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM ...
Page 187
... TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: TWCR TWINT TWEA TWSTA Value 1 X ATmega8535( Device 3 Device n ........ R1 TWSTO TWWC TWEN 1 ...
Page 188
... NOT ACK has been received 0x38 Arbitration lost in SLA+W or data bytes ATmega8535(L) 188 This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is gen- erated by writing the following value to TWCR: ...
Page 189
... Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave From master to slave From slave to master ATmega8535(L) A DATA A P $ $30 ...
Page 190
... Master Receiver Mode ATmega8535(L) 190 In the Master Receiver mode, a number of data bytes are received from a Slave Trans- mitter (see Figure 88). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered ...
Page 191
... Read data byte Read data byte 0 0 Read data byte Read data byte Read data byte 1 1 ATmega8535(L) TWSTO TWWC TWEN TWINT TWEA Next Action Taken by TWI Hardware 1 X SLA+R will be transmitted ACK or NOT ACK will be received 1 X SLA+R will be transmitted ...
Page 192
... Slave Receiver Mode ATmega8535(L) 192 Figure 89. Formats and States in the Master Receiver Mode MR Successfull S SLA R A reception from a slave receiver $08 $40 Next transfer started with a repeated start condition Not acknowledge A received after the slave address $48 Arbitration lost in slave address or data byte ...
Page 193
... SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR – does not reflect the last byte present on the bus when waking up from these sleep modes. ATmega8535(L) TWA4 TWA3 TWA2 TWA1 Device’ ...
Page 194
... Previously addressed with general call; data has been received; NOT ACK has been returned 0xA0 A STOP condition or repeated START condition has been received while still addressed as Slave ATmega8535(L) 194 Application Software Response To TWCR To/from TWDR STA STO TWINT No TWDR action or X ...
Page 195
... Reception of the general call General Call address and one or more data bytes Last data byte received is not acknowledged Arbitration lost as master and addressed as slave by general call From master to slave From slave to master ATmega8535( DATA A $60 $80 A $68 A DATA ...
Page 196
... Slave Transmitter Mode ATmega8535(L) 196 In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 92). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 92. Data Transfer in Slave Transmitter Mode ...
Page 197
... No TWDR action TWDR action TWDR action TWDR action 1 0 ATmega8535(L) TWINT TWEA Next Action Taken by TWI Hardware 1 0 Last data byte will be transmitted and NOT ACK should be received 1 1 Data byte will be transmitted and ACK should be re- ceived 1 0 Last data byte will be transmitted and NOT ACK should ...
Page 198
... Hardware 0xF8 No relevant state information available; TWINT = “0” 0x00 Bus error due to an illegal START or STOP condition ATmega8535(L) 198 Figure 93. Formats and States in the Slave Transmitter Mode Reception of the own S SLA R slave address and one or more data bytes ...
Page 199
... An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a Slave Receiver. Figure 95. An Arbitration Example Device 1 Device 2 MASTER MASTER TRANSMITTER TRANSMITTER SDA SCL ATmega8535(L) Master Receiver A Rs SLA REPEATED START Transmitted from slave to master V CC Device 3 ...
Page 200
... ATmega8535(L) 200 Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same Slave with different data or direction bit ...