PIC18F2331-E/MM Microchip Technology, PIC18F2331-E/MM Datasheet - Page 47

• Manufacturer Part Number: PIC18F2331-E/MM
• Description: IC MCU FLASH 4KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2331-E/MM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 768 B
• Data Rom Size: 256 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 5
• Height: 0.88 mm
• Interface Type: EUSART, I2C, SPI, SSP
• Length: 6 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V, 5.8 V
• Supply Voltage (min): 3.9 V, 4.2 V
• Width: 6 mm
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PIC18F2331-E/ML; PIC18F2331-E/ML

5.0
The PIC18F2331/2431/4331/4431 devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
FIGURE 5-1:
 2010 Microchip Technology Inc.
Note 1: See
OSC1
MCLR
V
DD
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
RESET
Instruction
RESET
INTRC
OST/PWRT
Pointer
32 s
Stack
Table 5-1
Brown-out
( )_IDLE
V
Time-out
Detect
DD
Sleep
Reset
WDT
Rise
OST
PWRT
Stack Full/Underflow Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
for time-out situations.
MCLRE
10-Bit Ripple Counter
11-Bit Ripple Counter
POR Pulse
BOREN
1024 Cycles
65.5 ms
PIC18F2331/2431/4331/4431
This section discusses Resets generated by MCLR,
POR and BOR, and the operation of the various start-
up timers. Stack Reset events are covered in
Section 6.1.2.4 “Stack Full/Underflow
WDT Resets are covered in
Timer
A simplified block diagram of the On-Chip Reset Circuit
is shown in
(WDT)”.
Figure
5-1.
S
R
Section 23.2 “Watchdog
DS39616D-page 47
Q
Enable OST
Enable PWRT
Chip_Reset
Resets”.
(1)