PIC18F2331-E/MM Microchip Technology, PIC18F2331-E/MM Datasheet - Page 317

• Manufacturer Part Number: PIC18F2331-E/MM
• Description: IC MCU FLASH 4KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2331-E/MM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 768 B
• Data Rom Size: 256 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 5
• Height: 0.88 mm
• Interface Type: EUSART, I2C, SPI, SSP
• Length: 6 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V, 5.8 V
• Supply Voltage (min): 3.9 V, 4.2 V
• Width: 6 mm
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PIC18F2331-E/ML; PIC18F2331-E/ML

RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
 2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
REG
W
REG
W
REG
Q1
=
=
=
=
=
=
register ‘f’
Rotate Right f (No Carry)
[ label ]
0  f  255
d  [0,1]
a  [0,1]
(f<n>)  dest<n – 1>,
(f<0>)  dest<7>
N, Z
The contents of register, ‘f’, are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register, ‘f’. If ‘a’ is ‘0’,
the Access Bank will be selected, over-
riding the BSR value. If ‘a’ is ‘1’, then
the bank will be selected as per the
BSR value.
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
1110 1011
?
1101 0111
1110 1011
1101 0111
RRNCF
REG, 1, 0
REG, W
00da
Process
Data
Q3
register f
f [,d [,a]]
ffff
destination
Write to
PIC18F2331/2431/4331/4431
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ‘f’
Set f
[ label ] SETF
0  f  255
a [0,1]
FFh  f
None
The contents of the specified register
are set to FFh. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ is ‘1’, then the bank will
be selected as per the BSR value.
1
1
SETF
Read
0110
Q2
=
=
0x5A
0xFF
REG
100a
Process
Data
f [,a]
Q3
DS39616D-page 317
ffff
register ‘f’
Write
Q4
ffff