PIC18F87J11T-I/PT Microchip Technology, PIC18F87J11T-I/PT Datasheet - Page 149

• Manufacturer Part Number: PIC18F87J11T-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J11T-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Type: FLASH
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 68
• Ram Memory Size: 3930Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of Pwm: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164136 - DEVELOPMENT KIT FOR PIC18AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F87J11T-I/PTTR

TABLE 10-18: PORTH FUNCTIONS
© 2009 Microchip Technology Inc.
RH0/A16
RH1/A17
RH2/A18/
PMD7
RH3/A19/
PMD6
RH4/PMD3/
AN12/P3C/
C2INC
RH5/PMBE/
AN13/P3B/
C2IND
RH6/PMRD/
AN14/P1C/
C1INC
Legend:
Note 1:
Pin Name
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE<6:3>.
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
Function
PMBE
PMRD
PMD7
PMD6
PMD3
P3C
C2INC
C2IND
P1C
C1INC
P3B
AN12
AN13
AN14
RH0
RH1
RH2
RH3
RH4
RH5
RH6
A16
A17
A18
A19
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
Setting
TRIS
0
1
x
0
1
x
0
1
x
x
x
0
1
x
x
x
0
1
x
x
0
x
0
1
x
0
x
0
1
x
x
0
x
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
DIG
DIG
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
LATH<0> data output.
PORTH<0> data input.
External memory interface, address line 16. Takes priority over port data.
LATH<1> data output.
PORTH<1> data input.
External memory interface, address line 17. Takes priority over port data.
LATH<2> data output.
PORTH<2> data input.
External memory interface, address line 18. Takes priority over port data.
Parallel Master Port data out.
Parallel Master Port data input.
LATH<3> data output.
PORTH<3> data input.
External memory interface, address line 19. Takes priority over port data.
Parallel Master Port data out.
Parallel Master Port data input.
LATH<4> data output.
PORTH<4> data input.
Parallel Master Port data out.
Parallel Master Port data input.
A/D input channel 12. Default input configuration on POR; does not affect
digital output.
ECCP3 Enhanced PWM output, channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Comparator 2 input C.
LATH<5> data output.
PORTH<5> data input.
Parallel Master Port data byte enable.
A/D input channel 13. Default input configuration on POR; does not affect
digital output.
ECCP3 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Comparator 2 input D.
LATH<6> data output.
PORTH<6> data input.
Parallel Master Port read strobe.
Parallel Master Port read in.
A/D input channel 14. Default input configuration on POR; does not affect
digital output.
ECCP1 Enhanced PWM output, channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Comparator 1 input C.
PIC18F87J11 FAMILY
Description
DS39778D-page 149