ATTINY26-16PU Atmel, ATTINY26-16PU Datasheet - Page 89
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ATTINY26-16PU
Manufacturer Part Number
ATTINY26-16PU
Description
IC AVR MCU 2K 16MHZ IND 20-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY26-16PU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
2-Wire/ISP/SM-Bus/SPI/UART/USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
20PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
16 MHz
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1477K–AVR–08/10
Figure 48. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram (Figure 48.), a bus transfer involves the following steps:
1. The a start condition is generated by the master by forcing the SDA low line while the
2. In addition, the start detector will hold the SCL line low after the master has forced an
3. The master set the first bit to be transferred and releases the SCL line (C). The slave
4. After eight bits are transferred containing slave address and data direction (read or
5. If the slave is addressed it holds the SDA line low during the acknowledgment cycle
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 49. Start Condition Detector, Logic Diagram
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the PORTB0 bit to zero. Note that DDRB0 must be set to one for
the output to be enabled. The slave device’s start detector logic (Figure 49.) detects the
start condition and sets the USISIF flag. The flag can generate an interrupt if necessary.
negative edge on this line (B). This allows the slave to wake up from sleep or complete
its other tasks, before setting up the Shift Register to receive the address by clearing the
start condition flag and reset the counter.
samples the data and shift it into the serial register at the positive edge of the SCL clock.
write), the slave counter overflows and the SCL line is forced low (D). If the slave is not
the one the master has addressed it releases the SCL line and waits for a new start
condition.
before holding the SCL line low again (i.e., the Counter Register must be set to 14 before
releasing SCL at (D)). Depending of the R/W bit the master or slave enables its output. If
the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line)
The slave can hold the SCL line low after the acknowledge (E).
by the master (F). Or a new start condition is given.
SDA
SCL
Write( USISIF)
A B
S
C
ADDRESS
SDA
SCL
1 - 7
R/W
8
D
ACK
9
E
DATA
1 - 8
D Q
CLR
ACK
9
D Q
CLR
DATA
1 - 8
USISIF
CLOCK
HOLD
ACK
9
P
F
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