ATTINY26-16PU Atmel, ATTINY26-16PU Datasheet - Page 119
![IC AVR MCU 2K 16MHZ IND 20-DIP](/photos/6/80/68043/313-20-dip_sml.jpg)
ATTINY26-16PU
Manufacturer Part Number
ATTINY26-16PU
Description
IC AVR MCU 2K 16MHZ IND 20-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY26-16PU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
2-Wire/ISP/SM-Bus/SPI/UART/USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
20PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
16 MHz
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1477K–AVR–08/10
Figure 65. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 66. Parallel Programming Timing, Reading Sequence (Within the Same Page) with Tim-
ing Requirements
Note:
PAGEL/BS1
XA1/BS2
PAGEL/BS1
XTAL1
DATA
1. The timing requirements shown in Figure 64 (i.e., t
1. The timing requirements shown in Figure 64 (i.e. t
XA1/BS2
XA0
OE
XTAL1
DATA
XA0
operation.
operation.
()
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
t
XLOL
t
OLDV
t
XLXH
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
(LOW BYTE)
DATA (Low Byte)
READ DATA
t
XLXH
t
BHDV
DVXH
DVXH
(HIGH BYTE)
LOAD DATA
DATA (High Byte)
, t
(HIGH BYTE)
, t
READ DATA
DATA (High Byte)
XHXL
XHXL
, and t
, and t
t
XLXH
t
OHDZ
XLDX
XLDX
LOAD ADDRESS
) also apply to reading
) also apply to loading
(LOW BYTE)
LOAD ADDRESS
ADDR1 (Low Byte)
(LOW BYTE)
ADDR1 (Low Byte)
(1)
119
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