ATTINY26L-8PU Atmel, ATTINY26L-8PU Datasheet - Page 72

• Manufacturer Part Number: ATTINY26L-8PU
• Description: IC MCU AVR 2K 5V 8MHZ 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: 2-Wire/ISP/SM-Bus/SPI/UART/USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Controller Family/series: AVR Tiny
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATTINY26L-8PJ; ATTINY26L-8PJ

Timer/Counter1 – TCNT1
Timer/Counter1 Output
Compare RegisterA – OCR1A
72
ATtiny26(L)
• Bits 3..0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
Table 34. Timer/Counter1 Prescale Select
The Stop condition provides a Timer Enable/Disable function.
This 8-bit register contains the value of Timer/Counter1.
Timer/Counter1 is realized as an up counter with read and write access. Due to syn-
chronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by
one CPU clock cycle in synchronous mode and at most two CPU clock cycles for asyn-
chronous mode.
The Output Compare Register A is an 8-bit read/write register.
The Timer/Counter Output Compare Register A contains data to be continuously com-
pared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A
compare match does only occur if Timer/Counter1 counts to the OCR1A value. A soft-
Bit
$2E ($4E)
Read/Write
Initial Value
Bit
$2D ($4D)
Read/Write
Initial Value
CS13
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CS12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MSB
MSB
R/W
R/W
7
0
7
0
CS11
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
R/W
6
0
6
0
CS10
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
R/W
5
0
5
0
Description
Asynchronous Mode
Timer/Counter1 is stopped.
PCK
PCK/2
PCK/4
PCK/8
PCK/16
PCK/32
PCK/64
PCK/128
PCK/256
PCK/512
PCK/1024
PCK/2048
PCK/4096
PCK/8192
PCK/16384
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
Description
Synchronous Mode
Timer/Counter1 is stopped.
CK
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
CK/128
CK/256
CK/512
CK/1024
CK/2048
CK/4096
CK/8192
CK/16384
R/W
R/W
1
0
1
0
LSB
R/W
LSB
R/W
0
0
0
0
1477F–AVR–12/04
OCR1A
TCNT1