ATTINY26L-8PU Atmel, ATTINY26L-8PU Datasheet - Page 58

• Manufacturer Part Number: ATTINY26L-8PU
• Description: IC MCU AVR 2K 5V 8MHZ 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: 2-Wire/ISP/SM-Bus/SPI/UART/USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Controller Family/series: AVR Tiny
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATTINY26L-8PJ; ATTINY26L-8PJ

Interrupt Handling
Interrupt Response Time
General Interrupt Mask
Register – GIMSK
58
ATtiny26(L)
The ATtiny26(L) has two 8-bit Interrupt Mask Control Registers; GIMSK – General Inter-
rupt Mask Register and TIMSK – Timer/Counter Interrupt Mask Register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction – RETI – is executed.
When the Program Counter is vectored to the actual Interrupt Vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag
bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software.
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After the four clock cycles the program vector address for the actual interrupt
handling routine is executed. During this four clock cycle period, the Program Counter
(10 bits) is pushed onto the Stack. The vector is a relative jump to the interrupt routine,
and this jump takes two clock cycles. If an interrupt occurs during execution of a multi-
cycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (10 bits) is popped back from the Stack. When AVR
exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served. Note that the Status Register – SREG
– is not handled by the AVR hardware, neither for interrupts nor for subroutines. For the
routines requiring a storage of the SREG, this must be performed by user software.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
Bit
$3B ($5B)
Read/Write
Initial Value
$00B
…
R
7
–
0
…
INT0
R/W
6
0
sei
…
PCIE1
R/W
5
0
…
PCIE0
R/W
4
0
R
3
–
0
R
2
–
0
R
1
–
0
R
0
–
0
1477F–AVR–12/04
GIMSK