ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 317
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.24.8.2
6.24.8.3
9111H–AUTO–01/11
Data Polling Flash
Data Polling EEPROM
When a page is being programmed into the Flash, reading an address location within the page
being programmed will give the value 0xFF. At the time the device is ready for a new page, the
programmed value will read correctly. This is used to determine when the next page can be
written. Note that the entire page is written simultaneously and any address within the page
can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when pro-
gramming this value, the user will have to wait for at least t
next page. As a chip-erased device contains 0xFF in all locations, programming of addresses
that are meant to contain 0xFF, can be skipped. See
value.
When a new byte has been written and is being programmed into EEPROM, reading the
address location being programmed will give the value 0xFF. At the time the device is ready
for a new byte, the programmed value will read correctly. This is used to determine when the
next byte can be written. This will not work for the value 0xFF, but the user should have the fol-
lowing in mind: As a chip-erased device contains 0xFF in all locations, programming of
addresses that are meant to contain 0xFF, can be skipped. This does not apply if the
EEPROM is re-programmed without chip erasing the device.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte
5. The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
In this case, RESET must be given a positive pulse of at least two CPU clock cycles
duration after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not,
all four bytes of the instruction must be transmitted. If the 0x53 did not echo back,
give RESET a positive pulse and issue a new Programming Enable command.
at a time by supplying the 6 LSB of the address and data together with the Load Pro-
gram Memory Page instruction. To ensure correct loading of the page, the data low
byte must be loaded before data high byte is applied for a given address. The Pro-
gram Memory Page is stored by loading the Write Program Memory Page instruction
with the 8 MSB of the address. If polling is not used, the user must wait at least
t
serial programming interface before the Flash write operation completes can result in
incorrect programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user
must wait at least t
318). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
WD_FLASH
CC
power off.
before issuing the next page (see
WD_EEPROM
before issuing the next byte (see
Atmel ATA6612/ATA6613
Table 6-127 on page
Table 6-127 on page 318
WD_FLASH
Table 6-127 on page
before programming the
318). Accessing the
for t
WD_FLASH
317
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