ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 316
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.24.8.1
316
Atmel ATA6612/ATA6613
Serial Programming Algorithm
Figure 6-126. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed program-
ming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the Atmel
of SCK.
When reading data from the Atmel ATA6612/ATA6613, data is clocked on the falling edge of
SCK. See
To program and verify the Atmel ATA6612/ATA6613 in the serial programming mode, the fol-
lowing sequence is recommended (see four byte instruction formats in
318):
1. Power-up sequence:
Apply power between V
systems, the programmer can not guarantee that SCK is held low during power-up.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to
2. V
Figure 6-127 on page 318
the XTAL1 pin.
CC
- 0.3V <
MISO
MOSI
SCK
AV
CC
< V
CC
ck
ck
CC
and GND while RESET and SCK are set to “0”. In some
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
+ 0.3V, however,
RESET
GND
XTAL1
®
for timing details.
ATA6612/ATA6613, data is clocked on the rising edge
(1)
AV
AVCC
CC
VCC
should always be within 1.8V - 5.5V
+2.7V to 5.5V
+2.7V to 5.5V
ck
ck
>= 12MHz
>= 12MHz
Table 6-128 on page
(2)
9111H–AUTO–01/11
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