ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 224
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.18.5
224
Atmel ATA6612/ATA6613
Data Transfer
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in
the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation
of the TxDn pin is overridden and given the function as the Transmitter's serial output.
Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register
to one. When the receiver is enabled, the normal pin operation of the RxDn pin is overridden
and given the function as the Receiver's serial input. The XCKn will in both cases be used as
the transfer clock.
After initialization the USART is ready for doing data transfers. A data transfer is initiated by
writing to the UDRn I/O location. This is the case for both sending and receiving data since the
transmitter controls the transfer clock. The data written to UDRn is moved from the transmit
buffer to the shift register when the shift register is ready to send a new frame.
Note:
The following code examples show a simple USART in MSPIM mode transfer function based
on polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag.
The USART has to be initialized before the function can be used. For the assembly code, the
data to be sent is assumed to be stored in Register R16 and the data received will be available
in the same register (R16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,
before loading it with new data to be transmitted. The function then waits for data to be present
in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the
value.
To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register
must be read once for each byte transmitted. The input buffer operation is identical to normal
USART mode, i.e. if an overflow occurs the character last received will be lost, not the first data
in the buffer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and
the UDRn is not read before all transfers are completed, then byte 3 to be received will be lost,
and not byte 1.
9111H–AUTO–01/11
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