ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 182
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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182
Atmel ATA6612/ATA6613
• Bit 5 – AS2: Asynchronous Timer/Counter2
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When
AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the
Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of
TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes
set. When TCNT2 has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated
with a new value.
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes
set. When OCR2A has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated
with a new value.
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes
set. When OCR2B has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated
with a new value.
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes
set. When TCCR2A has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be
updated with a new value.
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes
set. When TCCR2B has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be
updated with a new value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy
flag is set, the updated value might get corrupted and cause an unintentional interrupt to
occur.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are differ-
ent. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B,
TCCR2A and TCCR2B the value in the temporary storage register is read.
9111H–AUTO–01/11
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