ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 153
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.14.9
9111H–AUTO–01/11
Timer/Counter Timing Diagrams
The extreme values for the OCR1x Register represents special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be set to high
for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A out-
put will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
OCF1x.
Figure 6-49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 6-50
Figure 6-50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
(clk
(clk
OCRnx
TCNTn
OCFnx
TCNTn
OCRnx
OCFnx
clkTn
clkTn
clk
I/O
clk
I/O
/1)
/8)
I/O
I/O
shows the same timing data, but with the prescaler enabled.
OCRnx - 1
OCRnx - 1
Figure 6-49
OCRnx
OCRnx
OCRnx Value
OCRnx Value
Atmel ATA6612/ATA6613
shows a timing diagram for the setting of
OCRnx + 1
OCRnx + 1
T1
) is therefore shown as a
OCRnx + 2
OCRnx + 2
clk_I/O
/8)
153
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