ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 241
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.19.6.5
6.19.6.6
9111H–AUTO–01/11
TWI (Slave) Address Register – TWAR
TWI (Slave) Address Mask Register – TWAMR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multi master systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is
an associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
Figure 6-86. TWI Address Match Logic, Block Diagram
• Bits 7..1 – TWA: TWI (Slave) Address Register
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
• Bits 7..1 – TWAM: TWI Address Mask
• Bit 0 – Res: Reserved Bit
Initial Value
Initial Value
Read/Write
Read/Write
These seven bits constitute the slave address of the TWI unit.
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR
can mask (disable) the corresponding address bits in the TWI Address Register (TWAR).
If the mask bit is set to one then the address match logic ignores the compare between the
incoming address bit and the corresponding bit in TWAR.
match logic in detail.
This bit is an unused bit in the Atmel
Bit
Bit
TWA6
R/W
R/W
7
1
7
0
TWAMR0
Address
TWAR0
Bit 0
TWA5
R/W
R/W
6
1
6
0
Address Bit Comparator 6..1
TWA4
R/W
R/W
5
1
5
0
Address Bit Comparator 0
TWAM[6:0]
®
TWA3
R/W
R/W
ATA6612/ATA6613, and will always read as zero.
4
1
4
0
Atmel ATA6612/ATA6613
TWA2
R/W
R/W
3
1
3
0
TWA1
R/W
R/W
2
1
2
0
Figure 6-86
TWA0
R/W
R/W
1
1
1
0
Address
Match
shown the address
TWGCE
R/W
R
0
0
0
–
0
TWAMR
TWAR
241
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