ATMEGA16A-AUR Atmel, ATMEGA16A-AUR Datasheet - Page 20

• Manufacturer Part Number: ATMEGA16A-AUR
• Description: MCU AVR 16KB FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6.2
7.6.3
20
ATmega16A
EEDR – The EEPROM Data Register
EECR – The EEPROM Control Register
• Bits 15:9 – Res: Reserved Bits
These bits are reserved bits in the ATmega16A and will always read as zero.
• Bits 8:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
• Bits 7:0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega16A and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEWE bit must be written to one to write the value into the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-
erwise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
MSB
R/W
R
7
0
7
–
0
R/W
R
6
–
0
6
0
–
R/W
R
5
–
0
5
0
EEARH and EEARL – specify the EEPROM address in the
R/W
R
4
–
0
4
0
EERIE
R/W
R/W
3
0
3
0
EEMWE
R/W
R/W
2
0
2
0
EEWE
R/W
R/W
X
1
0
1
EERE
LSB
R/W
R/W
0
0
0
0
8154B–AVR–07/09
EECR
EEDR