PIC16F1934-E/ML Microchip Technology, PIC16F1934-E/ML Datasheet - Page 322

• Manufacturer Part Number: PIC16F1934-E/ML
• Description: IC PIC MCU FLASH 256KX7 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1934-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART/MI2C/SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F193X/LF193X
22.7
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register (Register 22-6).
When a write occurs to SSPBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 22-36 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 22-37:
TABLE 22-3:
DS41364A-page 320
Note 1:
Note: Values of 0x00, 0x01 and 0x02 are not valid
2:
BAUD RATE GENERATOR
for SSPADD when used as a Baud Rate
Generator for I
limitation.
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
SPI mode only.
F
OSC
2
C interface does not conform to the 400 kHz I
MSSP CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C. This is an implementation
SSPM<3:0>
SCL
2
C and SPI Master
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
SSPM<3:0>
F
CY
Control
Reload
Preliminary
SSPCLK
Reload
2
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
Table 22-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 22-1:
C specification (which applies to rates greater than
BRG Down Counter
SSPADD<7:0>
BRG Value
0Ch
13h
19h
4Fh
09h
27h
09h
00h
F
CLOCK
=
© 2008 Microchip Technology Inc.
----------------------------------------------
(
SSPADD
F
OSC
(2 Rollovers of BRG)
/2
F
OSC
400 kHz
400 kHz
250 kHz
+
308 kHz
100 kHz
308 kHz
100 kHz
100 kHz
F
CLOCK
1
) 4 ( )
(1)
(1)
(2)