PIC16F1934-E/ML Microchip Technology, PIC16F1934-E/ML Datasheet - Page 288

• Manufacturer Part Number: PIC16F1934-E/ML
• Description: IC PIC MCU FLASH 256KX7 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1934-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART/MI2C/SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F193X/LF193X
22.3.8
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• from Sleep, in Slave mode
• from Idle, in Slave or Master mode
TABLE 22-1:
DS41364A-page 286
APFCON
INTCON
PIE1
PIR1
SSPBUF
SSPCON1
SSPCON3
SSPSTAT
TRISA
TRISC
Legend:
Name
*
OPERATION IN POWER-MANAGED
MODES
Shaded cells are not used by the MSSP in SPI mode.
Page provides register information.
Synchronous Serial Port Receive Buffer/Transmit Register
TMR1GIE
TMR1GIf
ACKTIM
TRISC7
TRISA7
WCOL
Bit 7
SMP
GIE
REGISTERS ASSOCIATED WITH SPI OPERATION
—
CCP3SEL
TRISA6
TRISC6
SSPOV
ADIE
PCIE
Bit 6
PEIE
ADIF
CKE
T1GSEL
TMR0IE
TRISA5
TRISC5
SSPEN
RCIE
RCIF
SCIE
Bit 5
D/A
P2BSEL
Preliminary
TRISC4
TRISA4
BOEN
INTE
TXIE
Bit 4
TXIF
CKP
P
SRNQSEL C2OUTSEL
TRISA3
TRISC3
SSPM3
SDAHT
SSPIE
SSPIF
IOCIE
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
Bit 3
S
TMR0IF
CCP1IE
CCP1IF
TRISC2
SBCDE
TRISA2
SSPM2
Bit 2
R/W
data
to be
TMR2IE
TMR2IF
TRISA1
TRISC1
SSPM1
SSSEL
AHEN
Bit 1
INTF
© 2008 Microchip Technology Inc.
UA
shifted into
CCP2SEL
TMR1IE
TMR1IF
TRISA0
TRISC0
SSPM0
DHEN
IOCIF
Bit 0
BF
Register
the SPI
on Page
281*
277
279
276
84
73
74
77
86
94