AT90PWM1-16MU Atmel, AT90PWM1-16MU Datasheet - Page 199

• Manufacturer Part Number: AT90PWM1-16MU
• Description: IC AVR PWM 8KB FLASH 16MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM1-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.8.4.2
19.8.5
19.8.6
19.9
4378C–AVR–09/08
Amplifier
Digital Input Disable Register 0 – DIDR0
Digital Input Disable Register 1– DIDR1
ADLAR = 1
• Bit 7:0 – ADC7D..ADC0D: ACMP2:1 and ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
• Bit 5:0 – ACMP0D, AMP0+D, AMP0-D, ADC10D..ADC8D: ACMP0, AMP1:0 and ADC10:8
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
The AT90PWM1 features one differential amplified channel with programmable 5, 10, 20, and
40 gain stage.
On AT90PWM1, the amplifier has been improved in order to speed-up the conversion time.The
proposed improvement takes advantage of the amplifier characteristics to ensure a conversion
in less time.
In order to have a better understanding of the functioning of the amplifier synchronization, a tim-
ing diagram example is shown
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion
is started. In case the amplifier output is modified during the sample phase of the ADC, the on-
going conversion is aborted and restarted as soon as the output of the amplifier is stable. This
ensure a fast response time. The only precaution to take is to be sure that the trig signal (PSC)
frequency is lower than ADCclk/4.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Digital Input Disable
ADC7D
ADC9
ADC1
R/W
R
R
7
0
7
0
7
0
0
-
-
ADC6D
ADC8
ADC0
R/W
R
R
6
0
6
0
6
0
0
-
-
Figure 19-16
ACMP0D
ADC5D
ADC7
R/W
R/W
R
R
5
0
5
0
5
0
0
-
AMP0PD
ADC4D
ADC6
R/W
R/W
R
R
4
0
4
0
4
0
0
for AT90PWM1.
-
AMP0ND
ACMPM
ADC3D
ADC5
R/W
R/W
3
R
R
0
0
3
0
3
0
-
ACMP2D
ADC2D
ADC4
R/W
R
R
2
0
0
2
0
2
0
-
ADC1D
ADC3
R/W
R
R
1
0
0
1
0
1
0
-
AT90PWM1
ADC0D
ADC2
R/W
R
R
0
0
0
0
0
0
0
-
ADCH
ADCL
DIDR0
DIDR1
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