AT90PWM1-16MU Atmel, AT90PWM1-16MU Datasheet - Page 63
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AT90PWM1-16MU
Manufacturer Part Number
AT90PWM1-16MU
Description
IC AVR PWM 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM1-16SU.pdf
(297 pages)
Specifications of AT90PWM1-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.3
4378C–AVR–09/08
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os.
shows how the port pin control signals from the simplified
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 11-5. Alternate Port Functions
Note:
Table 8
11-5
the modules having the alternate function.
are not shown in the succeeding tables. The overriding signals are generated internally in
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
summarizes the function of the overriding signals. The pin and port indexes from
Pxn
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
SLEEP: SLEEP CONTROL
1
0
1
0
1
0
1
0
(1)
PUOExn
PUOVxn
PVOExn
PVOVxn
DIEOExn
DIEOVxn
SLEEP
DDOExn
DDOVxn
SYNCHRONIZER
D
L
SET
CLR
Q
Q
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
WDx: WRITE DDRx
WRx: WRITE PORTx
PUD: PULLUP DISABLE
WPx: WRITE PINx
clk
DIxn: DIGITAL INPUT PIN n ON PORTx
RDx: READ DDRx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
D
PINxn
I/O
CLR
Figure 11-2
: I/O CLOCK
Q
Q
RESET
RESET
PORTxn
Q
Q
DDxn
Q
Q
CLR
CLR
D
D
can be overridden by
1
0
AT90PWM1
clk
PUD
WDx
RDx
RRx
DIxn
AIOxn
RPx
I/O
WRx
Figure 11-5
PTOExn
WPx
Figure
I/O
63
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